iiinova — where your digital self keeps evolving

PypelineC @pipelinec.bsky.social · 25/09/2026

PypelineC fully open-source Xilinx 7-series FPGA flow made possible with fantastic tools like: Yosys + nextpnr-xilinx + Project X-Ray + openXC7. github.com/openxc7 #openxc7 Thanks to github user billiegoose for the PR!

github.com

openXC7

Free and open source FPGA toolchain for AMD/Xilinx Series 7 chips, including Kintex-7. Supports Kintex7 (including 325/420/480t), Artix7, Spartan7 and Zynq7. - openXC7

100

PypelineC @pipelinec.bsky.social · 08/09/2026

Check out the flashy new diagrams showing Pypeline HDL simulation with the Chili.CHIPS WireGuard project! github.com/JulianKemmer... #hardware #fpga #rtl #hls #eda

slide diagram of hdl sim and verification

101

PypelineC @pipelinec.bsky.social · 07/09/2026

PypelineC can work with alot of tools 😵‍💫 But getting started with open source GHDL, Yosys, PyRTL, and SKY130 based EDA flows is easier than ever with this Nix package 🤓 github.com/JulianKemmer... #FPGA #ASIC #hardware #opensource #RTL #HDL #HLS

022

PypelineC @pipelinec.bsky.social · 16/08/2026

Check out Garden of EDA: they very kindly have PypelineC and a bunch of other great tools listed 🤓 garden-of-eda.com

001

Reposted by PypelineC

Tom Dörr @tom-doerr.bsky.social · 02/08/2026

Runs WireGuard at full speed directly on an inexpensive Artix7 FPGA using entirely open-source tools without requiring a PC host or proprietary IP blocks.

111

PypelineC @pipelinec.bsky.social · 28/07/2026

Pypeline HDL makes verification as easy as Python. See ChaCha20-Poly1305 cryptography blocks in the Chili.CHIPS WireGuard FPGA design: github.com/JulianKemmerer/PipelineC/blob/master/examples/pypeline/chacha20poly1305/pypeline_sim_and_wireguard.md #hardware #fpga #rtl #hls #eda

101

PypelineC @pipelinec.bsky.social · 15/06/2026

Introducing Pypeline(HDL): new Python front end for PipelineC Very experimental, see: LLM assisted, but nonetheless seems to be working so far and I am excited. There are some generated docs here for basic overview stuff: github.com/JulianKemmer... and I am happy to answer questions too 🤓

220

PypelineC @pipelinec.bsky.social · 15/05/2026

A SoC in C? StreamSoC shows how to move from embedded C software to custom PipelineC hardware for doing things like realtime streaming data processing. youtu.be/dzF3okigyog

youtu.be

A SoC (System on Chip) in C? StreamSoC FPGA real-time audio video project

YouTube video by PipelineC

111

PypelineC @pipelinec.bsky.social · 28/03/2026

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

000

PypelineC @pipelinec.bsky.social · 13/03/2026

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

251

PypelineC @pipelinec.bsky.social · 10/03/2026

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions. github.com/JulianKemmer... #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

110

PypelineC @pipelinec.bsky.social · 13/02/2026

Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

110

PypelineC @pipelinec.bsky.social · 12/02/2026

Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources. github.com/JulianKemmer... #rtl #hls #verilog #vhdl #asic #eda

120

PypelineC @pipelinec.bsky.social · 03/01/2026

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com

010

PypelineC @pipelinec.bsky.social · 01/01/2026

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com

010

PypelineC @pipelinec.bsky.social · 26/12/2025

Advent of Code Day 4: video-like stream of 'pixel' data to a sliding 3x3 window via line buffer fifos. Auto pipeline for kernel function (counting neighbors), ~150M windows per sec. github.com/JulianKemmer... #fpga #rtl #hdl #hls #aoc25

github.com

020

PypelineC @pipelinec.bsky.social · 22/12/2025

Advent of Code Day 9: Iterates over RAM holding points. Autopipeline computes N rectangle areas per clock cycle and finds max. Easily does N=4 at ~100MHz with few pipeline stages, ~400M rect areas computed per sec 🎄 github.com/JulianKemmer... #fpga #rtl #hdl #hls #aoc25

github.com

010

PypelineC @pipelinec.bsky.social · 20/12/2025

Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz. ~1 Gbyte per sec of ascii could be processed 😎 🎄 github.com/JulianKemmer... #aoc25 #fpga #hdl #hls

github.com

010

PypelineC @pipelinec.bsky.social · 04/12/2025

Advent of Code 2025 Day 2 in FPGA 🤓 github.com/JulianKemmer... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com

010

PypelineC @pipelinec.bsky.social · 07/08/2025

"How do FPGAs execute blocking assignments in one clock cycle?" Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL. www.reddit.com/r/FPGA/comme... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

reddit.com

Software, FPGA Execution, a PipelineC response

021

Reposted by PypelineC

Catherine @whitequark.org · 22/05/2025

implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA glasgow-embedded.org/latest/apple...

glasgow-embedded.org

jtag-xvc - Glasgow Interface ExplorerContentsMenuExpandLight modeDark modeAuto light/dark, in light modeAuto light/dark, in dark mode

0253

Reposted by PypelineC

Jan Gray @jangray.bsky.social · 09/04/2025

#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing". insidehpc.com/2025/04/jaso... C-to-gates was a dream until Cong made it real.

1104

PypelineC @pipelinec.bsky.social · 14/03/2025

Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL ! #dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...

041

PypelineC @pipelinec.bsky.social · 20/02/2025

What can you do with reading arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes), write a little #python script that launches #GTKWave, and you have a tiny homemade cross platform logic analyzer thing! github.com/JulianKemmer...

capture of last 4 bytes of ethernet frame shown in gtkwave

031

PypelineC @pipelinec.bsky.social · 20/02/2025

#hardware debugging and wanted to see some #ethernet MAC address registers down in my pico-ice #ice40 #fpga design. Don't want manufacturer specific ILAs. Don't want to route signals to top, external #debug equipment I don't have. Just assign to #UART debug probe wire: github.com/JulianKemmer...

declaring and assigning debug probes code

110

PypelineC @pipelinec.bsky.social · 20/02/2025

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying so I have revived the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and will demo that on the pico ice

020

PypelineC @pipelinec.bsky.social · 14/02/2025

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi@mastodon.radio! #embedded #HDL #RTL #Verilog #VHDL #HLS github.com/JulianKemmer...

010

Reposted by PypelineC

Max Korbel @maxkorbel.bsky.social · 02/02/2025

👋 Hi, I’m Max! Principal Engineer @ Intel & lead of ROHD, an open-source project making hardware design more fun & accessible. Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech! #introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD

063

Reposted by PypelineC

Matt Venn @mattvenn.net · 18/01/2025

I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits. Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...

3226

PypelineC @pipelinec.bsky.social · 10/01/2025

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @raspberrypi.com. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

311

PypelineC @pipelinec.bsky.social · 08/01/2025

In the mood for the littlest bit of #FPGA #GameDev? 🤓 Check out this pico-ice based pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 github.com/JulianKemmer...

131

PypelineC @pipelinec.bsky.social · 26/12/2024

Gifted a new #FPGA dev board this season? 🤓 PipelineC aims to make #hardware description easier for #embedded folks. Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #hls github.com/JulianKemmer...

github.com

Dev Board Setup

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC

041

PypelineC @pipelinec.bsky.social · 15/12/2024

Part of why FPGAs are amazing is getting to be part of this hard 💪 hardware world while getting a relatively faster recompile and test cycle like software. I♥️#FPGA

030

Reposted by PypelineC

Matt Venn @mattvenn.net · 14/12/2024

To help others progress, I’m going to award several Christmas test gear grants. If you’re interested, apply here: www.zerotoasiccourse.com/post/test-eq...

zerotoasiccourse.com

Test Equipment Grant

Apply for a grant to spend on test equipment

43917

Reposted by PypelineC

Clash Language @clash-lang.bsky.social · 10/12/2024

Hello World! ✨ Clash is an open source functional hardware description language built on #Haskell, so if #FPGA, #ASIC and #Haskell are right up your alley, check out our website (link in bio) and give us a follow, we'll be posting more in the future :)

1155

PypelineC @pipelinec.bsky.social · 04/12/2024

If you like thinking like: computers are the best thing humans have ever invented, ~= ASICs are practically pinnacle of science/innovation etc then an FPGA on your desk at home is this magical window into literally the coolest thing humans have ever done ~ computer architecture / digital design 🤓

040

PypelineC @pipelinec.bsky.social · 30/11/2024

Have been super pleased with the ice40 #FPGA and #raspberrypi board that pico-ice.tinyvision.ai sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice 🤓 #HDL #Verilog #VHDL #hardware #embedded

pico-ice.tinyvision.ai

pico-ice: Main Page

130

PypelineC @pipelinec.bsky.social · 19/11/2024

😅😅😅😅😅😅😅😅😅 great post!

000

Reposted by PypelineC

Rachit Nigam @notypes.bsky.social · 19/11/2024

since more people are joining bluesky, time for a re-intro! i work on programming languages and compilers for hardware design and will be starting at MIT next year where i will lead the Foundations of Languages and Machines Lab (flame.csail.mit.edu). if the ideas excites you, reach out to me!

flame.csail.mit.edu

FLAME Lab @ MIT

2369

PypelineC @pipelinec.bsky.social · 19/11/2024

Hve you tried an alternative to #verilog or #vhdl? Not only does @thezoq2.bsky.social work on their own very cool Spade #rust inspired #HDL (and Surfer waveform viewer!) but they kindly have this awesome list to browse through too! 🤩 🤓 #fpga #rtl #asic #eda gitlab.com/TheZoq2/list...

030

Reposted by PypelineC

Catherine @whitequark.org · 15/11/2024

the RTL debugger i'm working on can now show diagnostics in-line in the source code :D

0428

Reposted by PypelineC

TheZoq2 @thezoq2.bsky.social · 19/11/2024

PipelineC is a really neat approach to HDL design! A lot of PipelineC is valid C and can be "simulated" by just running it, but where it makes sense it also has hardware specific semantics that make it very different from high level synthesis Oh, and the automatic pipelining is also very cool!

141

PypelineC @pipelinec.bsky.social · 18/11/2024

Enjoying dreaming of a world better than #Verilog or #VHDL? Come chat over on the #PipelineC Discord 🤓 Trying to make #HDL #RTL easier to write. Folks with #embedded experience, ever written #C for a #microcontroller with #hardware in mind, should feel right at home in #FPGA discord.gg/Aupm3DDrK2

011

PypelineC @pipelinec.bsky.social · 18/11/2024

Last week spoke at the first annual Soft #RISCV Systems Workshop 🔥 about a #hardware #SoC in #FPGA made using #PipelineC for doing #DSP computing #FFT with custom hardware. Can see slides here (no recording): docs.google.com/presentation... #RISC-V #eda #asic #hls #rtl #hdl #verilog #vhdl

fft soc diagram cpu stages and memory map peripherals

0102

PypelineC @pipelinec.bsky.social · 17/11/2024

'Shared Resource Buses': Multiple 'threads' of C function derived state machines share resources (memory, compute, etc) via AXI-like buses and arbitration. Reach out if you want to make something together! github.com/JulianKemmer... #rtl #hdl #hls #vhdl #verilog #asic #hardware #multithreaded #hpc

000

PypelineC @pipelinec.bsky.social · 17/11/2024

Use #PipelineC to listen to FM #radio with an #FPGA #SDR! Huge thanks to @dutracgi@mastodon.radio and @Darkknight512 for making first version a great learning experience. And @deepwavedigital for the fantastic hardware platform and workplace <3 #hardware #hdl #hls #asic github.com/JulianKemmer...

0122

Reposted by PypelineC

Stefan Abi-Karam @stefanabikaram.com · 10/11/2024

Prototype FPGA placer I wrote to learn Rust. Uses a really basic simulated annealing approach. Hope to integrate into an ongoing research project down the road. #fpga #eda #chipdesign stefanabikaram.com/writing/fpga...

1183