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PypelineC @pipelinec.bsky.social · 25/09/2026

PypelineC fully open-source Xilinx 7-series FPGA flow made possible with fantastic tools like: Yosys + nextpnr-xilinx + Project X-Ray + openXC7. github.com/openxc7 #openxc7 Thanks to github user billiegoose for the PR!

github.com

openXC7

Free and open source FPGA toolchain for AMD/Xilinx Series 7 chips, including Kintex-7. Supports Kintex7 (including 325/420/480t), Artix7, Spartan7 and Zynq7. - openXC7

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PypelineC @pipelinec.bsky.social · 08/09/2026

It's rare that Pypeline HDL native Python based simulation diverges from actual RTL sim. But we have a tool to help with that! With a nice new diagram too!

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PypelineC @pipelinec.bsky.social · 08/09/2026

Check out the flashy new diagrams showing Pypeline HDL simulation with the Chili.CHIPS WireGuard project! github.com/JulianKemmer... #hardware #fpga #rtl #hls #eda

slide diagram of hdl sim and verification

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PypelineC @pipelinec.bsky.social · 07/09/2026

PypelineC can work with alot of tools 😵‍💫 But getting started with open source GHDL, Yosys, PyRTL, and SKY130 based EDA flows is easier than ever with this Nix package 🤓 github.com/JulianKemmer... #FPGA #ASIC #hardware #opensource #RTL #HDL #HLS

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PypelineC @pipelinec.bsky.social · 16/08/2026

Check out Garden of EDA: they very kindly have PypelineC and a bunch of other great tools listed 🤓 garden-of-eda.com

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Reposted by PypelineC

Tom Dörr @tom-doerr.bsky.social · 02/08/2026

Runs WireGuard at full speed directly on an inexpensive Artix7 FPGA using entirely open-source tools without requiring a PC host or proprietary IP blocks.

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PypelineC @pipelinec.bsky.social · 28/07/2026

Pypeline HDL makes verification as easy as Python. See ChaCha20-Poly1305 cryptography blocks in the Chili.CHIPS WireGuard FPGA design: github.com/JulianKemmerer/PipelineC/blob/master/examples/pypeline/chacha20poly1305/pypeline_sim_and_wireguard.md #hardware #fpga #rtl #hls #eda

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PypelineC @pipelinec.bsky.social · 15/06/2026

Looking for any feedback yall have, and especially anyone wanting to give it a try to make something or contribute to the project 🤓

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PypelineC @pipelinec.bsky.social · 15/06/2026

So far single clock domains, registers, comb logic, autopipelining, global wires, and even a native simulator seem to be working! For ex. chasing the beam ray marched donut demo github.com/JulianKemmer... Python is the testbench for showing rendered frames and also what describes the hardware.

github.com

PipelineC/examples/pypeline/vga_donut.py at master · JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC

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PypelineC @pipelinec.bsky.social · 15/06/2026

Introducing Pypeline(HDL): new Python front end for PipelineC Very experimental, see: LLM assisted, but nonetheless seems to be working so far and I am excited. There are some generated docs here for basic overview stuff: github.com/JulianKemmer... and I am happy to answer questions too 🤓

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PypelineC @pipelinec.bsky.social · 15/05/2026

The StreamSoC demo is a fun music visualizer and video feedback experiment. But also is a reference for how easy PipelineC makes it to design your own SoC. Happy to help anyone give their own project a try! github.com/JulianKemmer...

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PypelineC @pipelinec.bsky.social · 15/05/2026

A SoC in C? StreamSoC shows how to move from embedded C software to custom PipelineC hardware for doing things like realtime streaming data processing. youtu.be/dzF3okigyog

youtu.be

A SoC (System on Chip) in C? StreamSoC FPGA real-time audio video project

YouTube video by PipelineC

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PypelineC @pipelinec.bsky.social · 28/03/2026

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

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PypelineC @pipelinec.bsky.social · 13/03/2026

Consider how no longer relying on closed source manufacturer specific proprietary HLS tools means this design can easily be used on any other FPGA platform. PipelineC allows the same design to be used across devices portably without needing human intervention to make pipelines meet timing.

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PypelineC @pipelinec.bsky.social · 13/03/2026

This Chili.CHIPS project focused on open source: * PipelineC: HLS-like auto-pipelining * Verilog-Ethernet: ETH networking IP library * OpenXC7: Xilinx 7 series PNR * VProc: System cosimulation with C/C++ interface * PeakRDL: SystemRDL control and status registers * SV2V: HDL converter

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PypelineC @pipelinec.bsky.social · 13/03/2026

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

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PypelineC @pipelinec.bsky.social · 10/03/2026

Already planning your better pipelined design on Latchup.app? Try describing your combinatorial logic in PipelineC? Or maybe you can contribute to making the compiler better? Come chat on Discord: discord.gg/9sWgH8gARY

latchup.app

Latchup - Competitive Programming for Hardware Description Languages

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PypelineC @pipelinec.bsky.social · 10/03/2026

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions. github.com/JulianKemmer... #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

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PypelineC @pipelinec.bsky.social · 13/02/2026

Existing libraries help: memory mapping is as simple as a struct. All stitched together with valid ready handshaking 'streams'. Writes done over StreamSoC's AXI-Lite like 'shared resource bus' that comes with helper FSMs github.com/JulianKemmer... #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

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PypelineC @pipelinec.bsky.social · 13/02/2026

Easy: draw_rect_t struct shared between embedded C software and PipelineC hardware. Mem mapped registers enqueue into command FIFO. Small hardware FSM reads from cmd FIFO does simple iteration to draw a rect of pixels. github.com/JulianKemmer... #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

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PypelineC @pipelinec.bsky.social · 13/02/2026

Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

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PypelineC @pipelinec.bsky.social · 12/02/2026

Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources. github.com/JulianKemmer... #rtl #hls #verilog #vhdl #asic #eda

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PypelineC @pipelinec.bsky.social · 03/01/2026

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com

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PypelineC @pipelinec.bsky.social · 01/01/2026

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com

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PypelineC @pipelinec.bsky.social · 26/12/2025

Advent of Code Day 4: video-like stream of 'pixel' data to a sliding 3x3 window via line buffer fifos. Auto pipeline for kernel function (counting neighbors), ~150M windows per sec. github.com/JulianKemmer... #fpga #rtl #hdl #hls #aoc25

github.com

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PypelineC @pipelinec.bsky.social · 22/12/2025

Advent of Code Day 9: Iterates over RAM holding points. Autopipeline computes N rectangle areas per clock cycle and finds max. Easily does N=4 at ~100MHz with few pipeline stages, ~400M rect areas computed per sec 🎄 github.com/JulianKemmer... #fpga #rtl #hdl #hls #aoc25

github.com

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PypelineC @pipelinec.bsky.social · 20/12/2025

Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz. ~1 Gbyte per sec of ascii could be processed 😎 🎄 github.com/JulianKemmer... #aoc25 #fpga #hdl #hls

github.com

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PypelineC @pipelinec.bsky.social · 04/12/2025

Advent of Code 2025 Day 2 in FPGA 🤓 github.com/JulianKemmer... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com

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PypelineC @pipelinec.bsky.social · 07/08/2025

"How do FPGAs execute blocking assignments in one clock cycle?" Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL. www.reddit.com/r/FPGA/comme... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

reddit.com

Software, FPGA Execution, a PipelineC response

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Reposted by PypelineC

Catherine @whitequark.org · 22/05/2025

implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA glasgow-embedded.org/latest/apple...

glasgow-embedded.org

jtag-xvc - Glasgow Interface ExplorerContentsMenuExpandLight modeDark modeAuto light/dark, in light modeAuto light/dark, in dark mode

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PypelineC @pipelinec.bsky.social · 28/04/2025

Heh not there yet 🤪 Leave it to awesome folks like this guy 😏 www.furygpu.com

furygpu.com

FuryGpu

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PypelineC @pipelinec.bsky.social · 28/04/2025

Yes that python running hardware has been all over this morning - super cool! Reminds me of some java/lisp machines from back in the day! Also saw this Python to Digital Logic work today too - reminds me a smidge of pipelinec 🤓 repository.lincoln.ac.uk/articles/con...

repository.lincoln.ac.uk

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PypelineC @pipelinec.bsky.social · 28/04/2025

Oh wow I didnt recall us speaking - but your post did remind me of that old desire for posix in hardware of some kind 🤓 Good to hear you are still around looking at cool things too!

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Reposted by PypelineC

Jan Gray @jangray.bsky.social · 09/04/2025

#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing". insidehpc.com/2025/04/jaso... C-to-gates was a dream until Cong made it real.

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PypelineC @pipelinec.bsky.social · 14/03/2025

Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL ! #dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...

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PypelineC @pipelinec.bsky.social · 09/03/2025

Will this (fpga+cpu+graphics) make it into a projectf tutorial somewhere? Seems like everyone wants to make their own GPU and this feels like a perfect intro 🤓

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PypelineC @pipelinec.bsky.social · 09/03/2025

yeah 'set the clock too high' build to evaluate fmax is something the pipelinec tool does as well. But be careful some tools, if given a large design with a goal too high they will give up early and you won't get representative fmax out.

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PypelineC @pipelinec.bsky.social · 09/03/2025

Id say its this reasoning that the tools don't tell you fmax. Most users have a target and just want to know if they made it there or not 🤷

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PypelineC @pipelinec.bsky.social · 05/03/2025

It's a C like HDL. So gets you into describing hardware without needing to learn verilog sensitivity lists and blocking non blocking etc. So just hopefully easier. And then has some fancier compiler things it can do: ex. help you pipeline for high performance designs 🤙

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PypelineC @pipelinec.bsky.social · 05/03/2025

Happen to know some basic C? If you are in the mood to experiment with getting right to hardware design and past the annoying Verilog/VHDL learning curve - happy to chat about PipelineC 🤓

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PypelineC @pipelinec.bsky.social · 20/02/2025

What can you do with reading arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes), write a little #python script that launches #GTKWave, and you have a tiny homemade cross platform logic analyzer thing! github.com/JulianKemmer...

capture of last 4 bytes of ethernet frame shown in gtkwave

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PypelineC @pipelinec.bsky.social · 20/02/2025

How does the hardware work? Probes can be in any clock domain and cdc to UART clock is handled for you with small FIFOs. Host PC control program read enable pulse causes hardware to respond over UART with the sample bytes from your debug probe. All included as a pipelinec library.

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PypelineC @pipelinec.bsky.social · 20/02/2025

How do you configure this? You define a type and a method for printing the data to console. The struct type is shared between software C and hardware PipelineC. Upon receiving bytes for your probe they are converted to your struct type and printed as specified.

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PypelineC @pipelinec.bsky.social · 20/02/2025

From there the bytes of probe data are shipped over UART to a host PC. A simple C program reading UART bytes displays your data:

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PypelineC @pipelinec.bsky.social · 20/02/2025

#hardware debugging and wanted to see some #ethernet MAC address registers down in my pico-ice #ice40 #fpga design. Don't want manufacturer specific ILAs. Don't want to route signals to top, external #debug equipment I don't have. Just assign to #UART debug probe wire: github.com/JulianKemmer...

declaring and assigning debug probes code

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PypelineC @pipelinec.bsky.social · 20/02/2025

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying so I have revived the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and will demo that on the pico ice

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