iiinova — where your digital self keeps evolving

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Matt Venn @mattvenn.net · 17/07/2026

The green traces show a chip designer’s worst nightmare! If they take too long to settle, it causes a serious problem that can’t be fixed after a chip is manufactured. Try out my updated metastability explorer tool here: zerotoasiccourse.com/metastability/

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Flux @willflux.bsky.social · 09/05/2026

Have you upgraded your @yosyshq.com yosys recently? #FPGA 0.49 (Jan 2025): TRELLIS_COMB: 4357 0.64 (May 2026): TRELLIS_COMB: 3682 15% LUT saving with no change in my Verilog design. 👏

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YosysHQ @yosyshq.com · 27/05/2026

$1200 too much for a Vivado license? How about: $0 - Yosys $0 - nextpnr $0 - OpenROAD $30 -Subnautica 2 $30 - Blahaj $180 - Glasgow interface explorer from @crowdsupply.bsky.social $950 -160kum^2 of Sky130 silicon + ASIC from @tinytapeout.com #opensource #FPGA #ASIC

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TinyTapeout @tinytapeout.com · 31/03/2026

Happy Trans day of visibility from a Tiny Tapeout ASIC!

ASIC plugged into a monitor showing the Trans flag

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YosysHQ @yosyshq.com · 12/02/2026

Join us in just over 3 hours for our 12th Yosys User's Group!

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YosysHQ @yosyshq.com · 09/02/2026

For our 12th Yosys User’s Group we’re inviting your questions! What have you always wanted to ask the team? - Formal verification - Synthesis - Plugins / internals - How to contribute - Roadmap Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 12th February.

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Matt Venn @mattvenn.net · 06/02/2026

At RF, your circuit stops being “small” compared to the signal - and everything changes. New video interview about RF design, VNAs, simulation, and on-chip antennas. www.youtube.com/watch?v=2xSA...

youtube.com

Simulating RF Reality: VNAs, OpenEMS, and an On-Chip Antenna Design with Ghaith

YouTube video by Zero To ASIC Course

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Breaking Taps @breakingtaps.com · 04/12/2025

The last month of my life: BreakingTTAPs This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space) I'll make a video at some point, but some high level details here:

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Matt Venn @mattvenn.net · 24/11/2025

What open source ASIC tools am I excited by in 2025? OpenEMS, 3D viewers, Surfer, OpenROAD, and lots more! Check this article for all the links: zerotoasiccourse.com/post/excited... #opensource #ASIC #tools

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YosysHQ @yosyshq.com · 31/10/2025

Ever wanted to try adding formal verification to your project but it seemed too hard or expensive to get started? In this video @mattvenn.net Venn shows you an easy way to get up and running with our open source tools and GitHub actions! youtu.be/Tn5wCOhzfvs #Verification #Formal #OpenSource

youtu.be

Formal Verification Adoption Made Easy - DVWorld Club

YouTube video by YosysHQ

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TinyTapeout @tinytapeout.com · 31/10/2025

You have just 10 days left to get your #ASIC design submitted to our TTSKY25b shuttle! There are still 70 early bird dev kits left, which mean you can do a full custom tapeout for just €185! Get started here: tinytapeout.com

tinytapeout.com

Tiny Tapeout - Tiny Tapeout

From idea to chip design in minutes! Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your designs manufactured on a real chip.

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YosysHQ @yosyshq.com · 09/10/2025

Starting in just over an hour! meet.jit.si/yosys-users-...

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YosysHQ @yosyshq.com · 08/10/2025

Join us tomorrow at 18:00 CEST!

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mlyoung @mlyoung101.bsky.social · 01/10/2025

this is me!! very much looking forward to presenting :3 please come join if you're interested in spaceflight/fault-tolerant computing or EDA algorithms! #yosys #eda

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YosysHQ @yosyshq.com · 29/09/2025

Our next #YUG will be with Matt Young, talking about triple modular redundancy. Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October. Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

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Bruno Levy @brunolevy01.bsky.social · 22/09/2025

Teaching processor design at Telecom Nancy Lesson 1: build your own risc-V processor at home using a FPGA Course notes are here: github.com/BrunoLevy/le...

Title slide: "adventures with FPGAs", with a composite background made of photos of FPGAs and peripherals

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Flux @willflux.bsky.social · 01/08/2025

Isle 🏝️ is my new #FPGA project. Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...

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TinyTapeout @tinytapeout.com · 25/07/2025

Want to help build a crowdsourced microcontroller? You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real! Take part for free! tinytapeout.com/competitions...

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YosysHQ @yosyshq.com · 09/06/2025

We have a new home for community discussion around Yosys yosyshq.discourse.group Join us there for questions, support and discussion about our open source EDA tools. #community #opensource #Yosys

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YosysHQ @yosyshq.com · 09/06/2025

We have a new home for community discussion around Yosys yosyshq.discourse.group Join us there for questions, support and discussion about our open source EDA tools. #community #opensource #Yosys

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TheZoq2 @thezoq2.bsky.social · 04/06/2025

Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer

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TheZoq2 @thezoq2.bsky.social · 03/06/2025

My thesis is now published online! 🎉 urn.kb.se/resolve?urn=...

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TinyTapeout @tinytapeout.com · 25/04/2025

IHP25b - our 4th open source chip with IHP is now open for digital design submissions! We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!

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TinyTapeout @tinytapeout.com · 15/04/2025

We’re close to making key decisions about future shuttles—and we want your input! 💬 What features matter most? What’s your price ceiling? Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P... 🎁 One respondent will win a beautiful 150mm silicon wafer!

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YosysHQ @yosyshq.com · 20/02/2025

Join us in a few hours for a talk about ASIC synthesis with Yosys! 18:00 CET / 22:30 IST / 09:00 PT meet.jit.si/yosys-users-...

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YosysHQ @yosyshq.com · 18/02/2025

It's time for another YUG! What's a YUG? It's the Yosys User's Group! For anyone interested in using Yosys - we've had sessions on primitives, plugins, hardware security, FPGAs and lots more... This time we'll be turning to #ASIC synthesis with our own Emil Jiří Tywoniak.

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Matt Venn @mattvenn.net · 03/02/2025

Simulation is the #ASIC terminology of the week! In the last month, Simulation has been the 35th most popular out of 42 terms.

zerotoasiccourse.com

Simulation

Simulation is the ASIC terminology of the week!

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YosysHQ @yosyshq.com · 03/02/2025

Looking for a tiny RISC-V core that scales with your needs? We covered FazyRV by Meinhard Kissich in our community spotlight last year: blog.yosyshq.com/p/community-... Now it's been silicon proven on @tinytapeout.com ! www.linkedin.com/posts/meinha...

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JauntyWunderKind @jauntywunderkind.bsky.social · 21/01/2025

Insta-follow, nice! Looking forward to your dive in to interesting off the main path of @yosyshq.com bit. Gonna have to figure out what other fpga/yosys/openfpga nerds there are to follow here that I'm missing!

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Flux @willflux.bsky.social · 21/01/2025

Working on a new #FPGA blog post this evening. I'll be sharing the draft with my sponsors in the next few days. @yosyshq.com "Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL, you're stuck running at the speed of your dev board oscillator..."

Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you're stuck running at the speed of your dev board oscillator. This post outlines the frequency capabilities of the ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies.

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Matt Venn @mattvenn.net · 18/01/2025

I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits. Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...

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Matt Venn @mattvenn.net · 19/01/2025

Very cool work by courk.cc ! Laser fault injection rig used to defeat RP2350 secure boot. Lovely writeup, interactive 3d model views, and uses the open source Glasgow FPGA multitool! courk.cc/rp2350-chall...

courk.cc

Laser Fault Injection on a Budget: RP2350 Edition

In August 2024, Raspberry Pi introduced the RP2350 microcontroller. This part iterates over the RP2040 and comes with numerous new features. These include security-related capabilities, such as a Secu...

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YosysHQ @yosyshq.com · 09/12/2024

Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes! Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST

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YosysHQ @yosyshq.com · 09/12/2024

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YosysHQ @yosyshq.com · 03/12/2024

At the beginning of the year Gabriel Gouvine wrote a guest blog post for us about his logic locking plugin for Yosys. He taped out a locked design on Tiny Tapeout 6 and we've just tested it! Blog: blog.yosyshq.com/p/logic-lock... youtu.be/m7MlQ2k8xC8

youtu.be

Logic Locking plugin on silicon works!

YouTube video by YosysHQ

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YosysHQ @yosyshq.com · 26/11/2024

After a summer break, our user group meetings have resumed again! In our last call, Katharina CeesaySeitz from ETH Zürich presented her work to detect microarchitectural information leakage via hardware timing side channels. Watch her talk on our Youtube channel! www.youtube.com/watch?v=Kxp-...

youtube.com

yug8

YouTube video by YosysHQ

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Maximo @maxiborga.bsky.social · 20/11/2024

Video of @mattvenn.net MPW1 chip

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