The post Community Motion: What Are RISC-V Advocates Doing? appeared first on RISC-V International.

Maven Silicon CEO P R Sivakumar on using RISC-V to bridge the skills gap, building a stronger engineering community and preparing new talent for an AI-driven semiconductor industry. The post <span class="vq-prefix">V Questions with… </span>Maven Silicon’s P R ‘Siva’ Sivakumar appeared first on RISC-V International.

The post Monte Cimone v3: Where RISC-V Stands in High-Performance Computing appeared first on RISC-V International.

'V Questions with…' uncovers the backstory to a RISC-V member's latest work in 5 questions. Here, I talk to the duo behind BER10, the sovereign SoC that Barcelona's Openchip taped out in under two years. The post <span class="vq-prefix">V Questions with… </span>Openchip’s Cesc Guim and Marc Fernández appeared first on RISC-V International.

MIPS’ Sameer Wasson explains why an automotive OEM’s choice of instruction set architecture (ISA) should prioritize supplier choice, software reuse and long-term economic control. The post For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice appeared first on RISC-V International.

The post World RISC-V Days: Tel Aviv Israel appeared first on RISC-V International.

The post World RISC-V Days: Gujarat India appeared first on RISC-V International.

The post World RISC-V Days: Boston USA appeared first on RISC-V International.

The post World RISC-V Days: Nairobi Africa appeared first on RISC-V International.

The post World RISC-V Days: Buenos Aires Argentina appeared first on RISC-V International.

The post World RISC-V Days: Graz Austria appeared first on RISC-V International.

The post World RISC-V Days: Mymensingh Bangladesh appeared first on RISC-V International.

The post World RISC-V Days: Dhaka Bangladesh appeared first on RISC-V International.

The post World RISC-V Days: Heraklion Greece appeared first on RISC-V International.

The post Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform appeared first on RISC-V International.

EDACrux, offered free to the RISC-V ecosystem, serves to demonstrate how success is built upon our members’ commitment to openness. The post Martin Fink’s Ferrite Engineering Lifts the Lid on ‘Schrödinger’s Instruction’ appeared first on RISC-V International.

The post Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW appeared first on RISC-V International.

The post RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses appeared first on RISC-V International.

The post Behind The Scenes of SHD Group’s 2026 RISC-V Market Forecast appeared first on RISC-V International.

Voting is now open for RISC-V International's Board of Directors. Learn how to nominate, understand board member responsibilities, and discover key election dates. The post Call for Candidates: Help Us Build a Board That Represents Our Entire Ecosystem appeared first on RISC-V International.

The RISC-V Ratified Specifications Library consolidates all of the available RISC-V specifications into one single, accessible repository. The post We Created a Single Source for All RISC-V Specifications appeared first on RISC-V International.

The post Docker on RISC-V: From Release to Production in 6 Days appeared first on RISC-V International.

The post Using a Performance Model to Implement a Superscalar CVA6 appeared first on RISC-V International.

Ahead of Embedded World, we explore what our members and co-exhibitors will showcase in Nuremberg, the common threads linking their work, and what this reveals about the embedded landscape in 2026. The post Production-Ready, Automotive-Grade, AI-Native: RISC-V at Embedded World 2026 appeared first on RISC-V International.

The post Support RAJA and Scientific Applications on RVV Architectures appeared first on RISC-V International.

The post RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual appeared first on RISC-V International.

<p>Porting Software to RISC-V (LFD114) is our free course for experienced engineers who need to move performance-critical software to RISC-V.</p> <p>The post <a href="https://riscv.org/blog/porting-software-riscv-course/">Start Porting Software To RISC-V Today With Our New, Free Online Course</a> appeared first on <a href="https://riscv.org">RISC-V International</a>.</p>

<p>The post <a href="https://riscv.org/blog/verifaix-ai-debug-agent/">VERIFAIX AI Debug Agent</a> appeared first on <a href="https://riscv.org">RISC-V International</a>.</p>

In this blog, Krste Asanović explains why in 2026, the state of the RISC-V union isn't just strong: it's stronger than ever. The post One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon appeared first on RISC-V International.

According to recent industry reporting, RISC-V has reached approximately 25% of the global processor market, reflecting growing adoption of open, modular architectures across embedded, automotive, data center, and emerging platforms.... The post RISC-V Hits 25% Market Share: The Rise of Open-Source Silicon Sovereignty appeared first on RISC-V International.

The post Announcing the 2025 AI & RISC-V Gemini Credit Recipients appeared first on RISC-V International.

The post World RISC-V Day: Beijing 2025 appeared first on RISC-V International.

newelectronics: Quintauris and Vector have partnered to integrate MICROSAR Classic into the RT-EUROPA real-time RISC-V automotive platform, giving developers a faster, standards-compliant path to building next-generation software-defined vehicles. The collaboration... The post newelectronics: Quintauris and Vector to integrate MICROSAR Classic on automotive RISC-V platform appeared first on RISC-V International.

The post Ocelot3: Full Vector “V” Extension for BOOM appeared first on RISC-V International.

Verification company Breker is well-versed in ensuring complex semiconductors stay robust in tough conditions, but space forced it to think differently. The post The Final Verification Frontier: How We Battle-Hardened RISC-V for Space appeared first on RISC-V International.

I have just returned from the 2025 RISC-V Industry Development Conference, held across Zhuhai and Macau. Guided by the 2025 theme “Accelerating Standardization, Facilitating Connection” and hosted by the RISC-V... The post Notes From the 2025 RISC-V Industry Development Conference appeared first on RISC-V International.

The post ChannelLife: Edge AI, security & RISC-V to redefine IoT chips by 2026 appeared first on RISC-V International.

The post Electronic Design: Checking Out the RISC-V Summit North America 2025 appeared first on RISC-V International.

The post Semiconductor Engineering: Why Openness Matters For AI At The Edge appeared first on RISC-V International.

Embecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This case study shows how the oneAPI Construction Kit lets you put this ecosystem on new hardware. The post Enabling High Performance RISC-V Software for AI in the Real World appeared first on RISC-V International.

As the dust settles on RISC-V Summit North America 2025, Tom Gall looks back at what he learned at his first RISC-V Summit since joining as VP of Technology. The post 7 Things I Learned at RISC-V Summit North America 2025 appeared first on RISC-V International.

Andes: d-Matrix and Andes have partnered to integrate Andes’ high-performance AX46MPV RISC-V CPU IP into d-Matrix’s next-generation Raptor accelerator, the first to feature 3D In-Memory Compute (3DIMC) technology for faster,... The post Andes: d-Matrix and Andes Team on World’s Highest Performing, Most Efficient Accelerator for AI Inference at Scale appeared first on RISC-V International.

EDN: RISC-V adoption in automotive applications is accelerating, with new partnerships and certified processor cores enabling software-defined vehicles and safety-critical systems. Collaborations among Quintauris, Andes, Lauterbach, Tenstorrent, and Codasip are... The post EDN: RISC-V Summit spurs new round of automotive support appeared first on RISC-V International.

WebProNews: RISC-V International has achieved Publicly Available Specification (PAS) Submitter status from ISO/IEC JTC1, marking a major step toward international standardization of its open instruction set architecture. This milestone positions... The post WebProNews: RISC-V’s ISO Milestone: Open ISA Poised for Global Dominance appeared first on RISC-V International.

I’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in the RISC-V HPC special interest... The post We’re Showcasing RISC-V at SC25, the World’s Largest Supercomputing Conference appeared first on RISC-V International.

EEWorldOnline: MIPS has begun sampling its new I8500 processor, a scalable, multithreaded data movement processor IP designed for real-time, event-driven computing across hyperscale, automotive, industrial, and communications markets. Optimized for... The post EEWorldOnline: MIPS releases multithreaded processor for edge computing appeared first on RISC-V International.

Open-technology veteran Gall will drive RISC-V International’s technical vision and collaboration strategy, strengthening the organisation’s push for worldwide adoption of the RISC-V ISA. The post RISC-V International Names Tom Gall as Vice President of Technology appeared first on RISC-V International.

EDN: At RISC-V Summit North America 2025, industry leaders unveiled the latest advances in CPU cores, vector processors, and AI-powered designs shaping the next wave of open computing. The event... The post EDN: The next RISC-V processor frontier: AI appeared first on RISC-V International.

All About Circuits: Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors. In a move aimed... The post All About Circuits: Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing appeared first on RISC-V International.

EETimes: Google Research has open-sourced its Coral NPU IP (previously codenamed Kelvin), which it is giving to the industry in a bid to accelerate edge AI implementations by reducing fragmentation and... The post EETimes: Google Open-Sources NPU IP, Synaptics Implements It appeared first on RISC-V International.