iiinova — where your digital self keeps evolving

Wow I need to check if auto correct goofed something... Putting = porting

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Just need someone to sell an old broken Steam VR kit so I can get the v2 lighthouses 😅

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Lattice ECP5, works with 25k size and up but if you want full support you need the 85k :) I'm putting old VHDL to Spade for the Harris/Shi-Thomasi feature extractor and multi level pyramids for the patch at the maxima if the feature. My aim is that this should become a 250-300g drone :D

You know when you get an idea, and start working on it ... and 70% in you ask yourself, what have I done? How will I ever finish this? When an idea wins ... 😅 Might as well finish the hardware right?

Schematic blocks in KiCAD. FPGA, FC, RGMII Ethernet, 8x cameras, lighthouse sensors, RPi CM5 ... over enthusiastic.

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It was a yosys issue, they don't do lowering to buffered BRAM, only combinatorial - not sure why though 🤔

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I saw this, I was thinking about getting JTAGG to work with it as a test :) with e.g. CH347 it's super easy to do custom JTAG stuff

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Tjenare! Fun to see you on Bluesky :D I'll upload it when a bit more done, feel free to take anything you want from it! The biggest issue I had was yosys not integrating the FFs into the BRAM so has to make a yosys plugin to detect and change the BRAM type.

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I need to implement a protocol and a debugging crate using nusb for the JTAGG block, UART debugging is it's own purgatory. I want dat RTT + defmt feeling, but on FPGAs :P

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Dion Dokter @diondokter.nl · 07/09/2026

A fun experiment, tried spade-lang.org and made an Ethernet stack running GbE with UDP and ARP support. Nice (Rust) feeling for an HDL, might migrate to it from Amaranth :D Tested on a Colorlight 5A 75B, ECP5 25F. The stack is about 5k LUTs/4k FF, the rest debugging, UART and MDIO scanning.

Colorlight board with Ethernet cable and CH347F JTAG

[INFO] Place and route maximum frequencies:
$glbnet$clk125: 131.4 MHz (target: 125 MHz)
$glbnet$clk25$TRELLIS_IO_IN: 57.4 MHz (target: 25 MHz)
$glbnet$clk_sys: 90.4 MHz (target: 62.5 MHz)
$glbnet$eth0_rx_clk$TRELLIS_IO_IN: 146.5 MHz (target: 125 MHz)
$glbnet$eth1_rx_clk$TRELLIS_IO_IN: 141.4 MHz (target: 125 MHz)
[INFO] Place and route components:
ALU54B: 0/14 (0.0%)
CLKDIVF: 0/4 (0.0%)
DCCA: 5/56 (8.9%)
DCSC: 0/2 (0.0%)
DCUA: 0/1 (0.0%)
DDRDLL: 0/4 (0.0%)
DLLDELD: 0/8 (0.0%)
DP16KD: 5/56 (8.9%)
DQSBUFM: 0/8 (0.0%)
DTR: 0/1 (0.0%)
ECLKBRIDGECS: 0/2 (0.0%)
ECLKSYNCB: 0/10 (0.0%)
EHXPLLL: 1/2 (50.0%)
EXTREFB: 0/1 (0.0%)
GSR: 0/1 (0.0%)
IOLOGIC: 22/128 (17.2%)
JTAGG: 0/1 (0.0%)
MULT18X18D: 0/28 (0.0%)
OSCG: 0/1 (0.0%)
PCSCLKDIV: 0/2 (0.0%)
SEDGA: 0/1 (0.0%)
SIOLOGIC: 0/69 (0.0%)
TRELLIS_COMB: 14481/24288 (59.6%)
TRELLIS_ECLKBUF: 0/8 (0.0%)
TRELLIS_FF: 10054/24288 (41.4%)
TRELLIS_IO: 34/197 (17.3%)
TRELLIS_RAMW: 0/3036 (0.0%)
USRMCLK: 1/1 (100.0%)

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Reposted by Emil Fresk / korken89

My async compiler work got funded! So here's my first PR: github.com/rust-lang/ru... Roughly, it changes match x { true => foo(1).await, false => foo(2).await, } to match x { true => foo(1), false => foo(2), }.await This means the future will only have 1 state instead of 2

github.com

Add merge yields by diondokter · Pull Request #162429 · rust-lang/rust

Part of Async statemachine optimisation project goal r? dingxiangfei2009 Added a pass that merges functionally identical yields right before the async StateTransform pass. The StateTransform pass c...

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Reposted by Emil Fresk / korken89

Simen E. Sørensen @simenzhor.bsky.social · 01/09/2026

Some hopefully interesting reflections on how the team at my day job made the world’s first functional safety certified product based on Rust. This was a massive undertaking, and I think some of you might appreciate it 🦀 #rust #rustlang #safety #functionalsafety www.sonair.com/journal/how-...

sonair.com

Sonair | Journal | How we developed the world's first safety-certified product written in Rust – and why we went bare metal

We just certified it. ADAR One is the first safety-certified embedded system built in Rust. I want to share how we got here, for other Rust developers who are looking at safety-critical work and wonde...

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Emil Fresk / korken89 @emilfresk.com · 22/06/2026

I find mdbook together with mdbook-xref, mdbook-abbr2, mdbook-bib, mdbook-mermaid, mdbook-figure preprocessors is a really nice foundation for technical documentation, even for complex referencing in large books where vanilla mdbook can get tedious (thanks to mdbook-xref).

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Reposted by Emil Fresk / korken89

Jonathan Pallant @thejpster.org.uk · 16/05/2026

I wanted to write about asynchrous time, but first I have to give you a history lesson: thejpster.org.uk/blog/blog-20...

thejpster.org.uk

JP's Website

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Emil Fresk / korken89 @emilfresk.com · 07/05/2026

Can you link it? :D My Reddit skills need backup

Emil Fresk / korken89 @emilfresk.com · 06/05/2026

This bites us every day, I'd wager the the time we spend optimizing for this would have paid for the compiler work 😅

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Reposted by Emil Fresk / korken89

Dion Dokter @diondokter.nl · 04/05/2026

Final part of my async blog! tweedegolf.nl/en/blog/237/... Last time I shared some tips for improving your async code. Now we look at why the compiler doesn't do it for us. I want to fix it in the compiler, but I need your help! If you can help with funding, reach out to me. Please share :)

tweedegolf.nl

Async Rust never left the MVP state - Blog - Tweede golf

I've previously explained async bloat and some work-arounds for it, but would much prefer to solve the issue at the root, in the compiler. I've submitted a Project Goal, and am looking for help to ...

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Reposted by Emil Fresk / korken89

Jonathan Pallant @thejpster.org.uk · 26/04/2026

Who's written a FIQ handler before?

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Reposted by Emil Fresk / korken89

Tweede golf @tweedegolf.bsky.social · 13/04/2026

Async Rust is amazing, but not flawless; async bloat is an issue. In this blog, @diondokter.nl explains the causes of async bloat, and some workarounds: tweedegolf.nl/en/blog/235/... #rustlang #embedded #async

tweedegolf.nl

Debloat your async Rust - Blog - Tweede golf

Async Rust is amazing, but far from flawless. In this blog, I'll walk you through the current struggles and possible solutions.

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Reposted by Emil Fresk / korken89

KiCad EDA @kicad.org · 20/03/2026

KiCad version 10 is out today! Lots of features, lots of speed. We hope you like it. www.kicad.org/blog/2026/03...

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Emil Fresk / korken89 @emilfresk.com · 04/03/2026

I need to compare again, or make ours open sooner 😅 I think our main take compared to others is the git based staleness and unfulfilledness analysis we do, so there is no need for anything expect an mdbook and code annotations. Hard to fit in a post, but giving it a go would answer most questions.

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Emil Fresk / korken89 @emilfresk.com · 02/03/2026

We're close to open up what we worked on, let's look for synergies then and maybe there can be some inspiration flow between the projects 🚀

Emil Fresk / korken89 @emilfresk.com · 02/03/2026

Yeah, that's on us - we should have opened issues on the tooling we evaluated when we encountered issues in them ...

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Emil Fresk / korken89 @emilfresk.com · 21/02/2026

Yeah the LSP is really nice we stole that idea directly for the developer experience :D

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Emil Fresk / korken89 @emilfresk.com · 21/02/2026

We also evaluated tracey, t-reqs, doorstop, mantra, ... All were sadly broken in their own way or based around a workflow for safety critical that did not work with our team/our git as source of truth for staleness analysis. So we built our own internal tool. I think we'll open it up soon.

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Reposted by Emil Fresk / korken89

FerrousSystems @ferroussystems.bsky.social · 18/02/2026

We're going to Nuremberg! You can find us at #EmbeddedWorld in Hall 4 at booth 4-402. Come say hi!

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Reposted by Emil Fresk / korken89

Jonathan Pallant @thejpster.org.uk · 16/02/2026

Bare-metal SMP Armv8-R AArch32 in Rust, ping ponging Software Generated Interrupts between cores using the Generic Interrupt Controller v3. I'm very happy to see this working. github.com/thejpster/aa...

github.com

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Emil Fresk / korken89 @emilfresk.com · 15/02/2026

That sounds like the sane pragmatic choice 👍👍

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Emil Fresk / korken89 @emilfresk.com · 09/02/2026

After poking the PL192 VIC registers in our Cortex-R5F for a few hours and wondering why nothing is happening (and no hardfaults 🤔), remember to double check that the vendor has not replaced the standard interrupt controller with their own 💔 Assumptions is the mother of all ... VIM != VIC

Emil Fresk / korken89 @emilfresk.com · 02/02/2026

*looking at TI safety critical MCU* applications: elevators, dangerous machinery, ..., game consoles, TV remote Huh

Emil Fresk / korken89 @emilfresk.com · 01/02/2026

I've wanted to try that, still waiting for a good project

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Emil Fresk / korken89 @emilfresk.com · 29/01/2026

Du you have any resource you recommend if one wants to try and make one?

Rust Language @rust-lang.org · 22/01/2026

Reposted by Emil Fresk / korken89

Rust 1.93.0 has been released! 🌈 🦀✨ This release includes a new musl version for the *-linux-musl targets, adds support for #[cfg] inside asm!(), and adds [T]::as_array, VecDeque::{pop_front_if, pop_back_if}, Vec/String::into_raw_parts, fmt::form_fn, and more! ✨ blog.rust-lang.org/2026/01/22/R...

blog.rust-lang.org

Announcing Rust 1.93.0 | Rust Blog

Empowering everyone to build reliable and efficient software.

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Emil Fresk / korken89 @emilfresk.com · 22/01/2026

It's been 0 days since I had to convince someone that CRC is not equivalent to encryption.

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Emil Fresk / korken89 @emilfresk.com · 30/12/2025

Do you have any nice standoff when there are components on the bottom side and want to preheat a board?

Dion Dokter @diondokter.nl · 20/12/2025

Reposted by Emil Fresk / korken89

Linkers for embedded kinda suck, no? Do you work at a big company who could use a new one? At @tweedegolf.bsky.social we have some amazing people who could build an awesome new embedded linker. We should talk.

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Emil Fresk / korken89 @emilfresk.com · 16/12/2025

Looks like a more modern Gerrit

Emil Fresk / korken89 @emilfresk.com · 05/12/2025

Oh this looks nice, is there somewhere one can follow this?

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A DSL which outputs kicad netlists would be a fun little project

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Parts could have their requirements, e.g. surrounding passives, differential pairs, length matching, current reoriented, ... encoded. And linters & CI could check that it's followed or a known "accept the risk of not following". I think the answer is "it's how it's always been done"

Sure one would want to sometimes view things, but that sounds like something that can be generated. And eventually one would trust the type system more and more.

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