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Emil Fresk / korken89

@emilfresk.com
1.2K followers 40 following 77 posts

PhD in Robotics, (embedded) Rust nerd, and embedded enthusiast. Develops and maintain rtic.rs.

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Emil Fresk / korken89 @emilfresk.com · 17h
I'm sure it will fit 😅🤡
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Emil Fresk / korken89 @emilfresk.com · 28/09/2026
:D Yeah, it's just using line buffers! For a more versatile board one might need external memory, but for now I've skipped it. The FPGA is quite full as is, so I need to drop something if it should fit 😅
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Emil Fresk / korken89 @emilfresk.com · 27/09/2026
So it begins...
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Emil Fresk / korken89 @emilfresk.com · 27/09/2026
You know when you get an idea, and start working on it ... and 70% in you ask yourself, what have I done? How will I ever finish this? When an idea wins ... 😅 Might as well finish the hardware right?
Schematic blocks in KiCAD. FPGA, FC, RGMII Ethernet, 8x cameras, lighthouse sensors, RPi CM5 ... over enthusiastic.
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Emil Fresk / korken89 @emilfresk.com · 19/09/2026
A fun experiment, tried spade-lang.org and made an Ethernet stack running GbE with UDP and ARP support. Nice (Rust) feeling for an HDL, might migrate to it from Amaranth :D Tested on a Colorlight 5A 75B, ECP5 25F. The stack is about 5k LUTs/4k FF, the rest debugging, UART and MDIO scanning.
Colorlight board with Ethernet cable and CH347F JTAG[INFO] Place and route maximum frequencies:
$glbnet$clk125: 131.4 MHz (target: 125 MHz)
$glbnet$clk25$TRELLIS_IO_IN: 57.4 MHz (target: 25 MHz)
$glbnet$clk_sys: 90.4 MHz (target: 62.5 MHz)
$glbnet$eth0_rx_clk$TRELLIS_IO_IN: 146.5 MHz (target: 125 MHz)
$glbnet$eth1_rx_clk$TRELLIS_IO_IN: 141.4 MHz (target: 125 MHz)
[INFO] Place and route components:
ALU54B: 0/14                (0.0%)
CLKDIVF: 0/4                (0.0%)
DCCA: 5/56                  (8.9%)
DCSC: 0/2                   (0.0%)
DCUA: 0/1                   (0.0%)
DDRDLL: 0/4                 (0.0%)
DLLDELD: 0/8                (0.0%)
DP16KD: 5/56                (8.9%)
DQSBUFM: 0/8                (0.0%)
DTR: 0/1                    (0.0%)
ECLKBRIDGECS: 0/2           (0.0%)
ECLKSYNCB: 0/10             (0.0%)
EHXPLLL: 1/2               (50.0%)
EXTREFB: 0/1                (0.0%)
GSR: 0/1                    (0.0%)
IOLOGIC: 22/128            (17.2%)
JTAGG: 0/1                  (0.0%)
MULT18X18D: 0/28            (0.0%)
OSCG: 0/1                   (0.0%)
PCSCLKDIV: 0/2              (0.0%)
SEDGA: 0/1                  (0.0%)
SIOLOGIC: 0/69              (0.0%)
TRELLIS_COMB: 14481/24288  (59.6%)
TRELLIS_ECLKBUF: 0/8        (0.0%)
TRELLIS_FF: 10054/24288    (41.4%)
TRELLIS_IO: 34/197         (17.3%)
TRELLIS_RAMW: 0/3036        (0.0%)
USRMCLK: 1/1              (100.0%)
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Emil Fresk / korken89 @emilfresk.com · 07/07/2026
Magical ✨
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Emil Fresk / korken89 @emilfresk.com · 16/10/2025
Ah yes, the radio test box that finds 99% of logic errors 😁 The kind of automated testing that can be done is an absolute treasure. Yankiness is included.
Radio test box filled with radio transceivers, and an oscilloscope on top
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Emil Fresk / korken89 @emilfresk.com · 28/08/2025
So, how yanky are your test setups at work sometimes? I'll start 😅
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Emil Fresk / korken89 @emilfresk.com · 28/11/2024
Next project! A signal recorder for our radio tracing test bench. Made to analyze 32 radios in our product in parallel.
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Emil Fresk / korken89 @emilfresk.com · 07/11/2024
Time for work to start on a new project :D
Partially mounted PCB in edge rails
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