iiinova — where your digital self keeps evolving

Flux @willflux.bsky.social · 10/10/2026

New (secondhand) book to help me develop 🏝️Isle.Computer floating point in #riscv asm. Subnormals seem much easier in software than hardware. 😄

Secondhand copy of Math Toolkit for Real-Time Programming by Jack W. Crenshaw.

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Flux @willflux.bsky.social · 04/10/2026

The lesser-known #Amstrad fondue computer. Does anyone know anything about its architecture?

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Flux @willflux.bsky.social · 26/09/2026

“The plot of the 1971 comedy film Lady Liberty, starring Sophia Loren, is based on the United States ban on mortadella.”

Poster for the film Lady Liberty. Showing Sophia Loren as dressed as the Statue of Liberty holding with sausages.

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Flux @willflux.bsky.social · 12/09/2026

New draft 🏝️ Isle.Computer blog post: projectf.io/isle/graphic... “This post is a tale of two devices: Display and Earthrise. These graphic devices make the graphics CPU programmable for the first time.“ #FPGA

ULX3S dev board driving computer display showing randomly positioned concentric blue circles.

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Flux @willflux.bsky.social · 22/08/2026

With scroll hardware registers fixed, here’s a demo of draw and display scrolling hardware. #ULX3S #FPGA

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Flux @willflux.bsky.social · 17/08/2026

Looking forward to seeing Arcadia on the stage for the first time.

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Flux @willflux.bsky.social · 16/08/2026

Looks like I've found a real hardware rendering bug. I've only tested this in Verilator/SDL sim so far, but time for me for me to call it a night. I can check it on FPGA when I'm back at my desk. 😴

Concentric filled circles with some vertical columns of pixels moved a few pixels up or down from the correct position.

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Flux @willflux.bsky.social · 13/08/2026

It's too hot to think clearly. 🥵 While working on my hardware graphics engine, I was dismayed to discover a new hardware scrolling bug. On closer inspection it turns out to be an error in my RISC-V asm. ☺️ You can see the broken version running here in simulation.

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Flux @willflux.bsky.social · 11/08/2026

Testing CPU control of the Earthrise graphics engine. Open source designs running on an ECP5 #FPGA.

ULX3S FPGA dev board driving widescreen monitor. The RISC-V CPU running on the FPGA is controlling the Earthrise graphics engine (also running on the FPGA). The monitor displaying many overlapping concentric rings in three shades of blue.

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Flux @willflux.bsky.social · 05/08/2026

The Earthrise drawing engine assembler now outputs memory offsets and the mnemonics assembled. The drawing engine uses 16-bit instructions, but a 32-bit bus to match the 32-bit RISC-V CPU. While I'm big endian at (68K) heart, Earthrise is little endian to match RISC-V.

Earthrise assembler source (extract):

# line colours
lca 10
lcb 8

# line 0
x0 32
y0 0
x1 223
y1 191
draw line ca

Earthrise instructions assembled (extract):

C108C00A // 0000: lca 10; lcb 8
10000020 // 0004: x0 32; y0 0
30BF20DF // 0008: x1 223; y1 191
00DFD100 // 000C: draw line ca; x0 223

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Flux @willflux.bsky.social · 03/08/2026

Oh no, there's a translation bug in my hardware 2D drawing engine... wait no, my docs aren't clear enough (even to me). Translation only affects coordinates set *after*. 😮‍💨 Docs revised. Now I can move onto CPU controlled animation testing.

Isle.Computer running in simulation showing blue concentric rings drawn in the centre of the display.

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Flux @willflux.bsky.social · 30/07/2026

Done a bit of work on the 🏝️ Isle.Computer graphics devices today. Here's a 16 colour compositor test running under simulation. #FPGA

16-colour image of purple crocuses overlaid with geometric shapes and text displaying "Isle.Computer" and the resolution of different components.

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Flux @willflux.bsky.social · 26/07/2026

It’s raining! 🌧️ It’s been so long, I’ve almost forgotten what rain is. Europe is very dry this summer.

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Flux @willflux.bsky.social · 25/07/2026

🏝️ Isle.Computer doesn't have interrupts yet, but catching bus faults is still handy, especially when running software under Verilator simulation. Here's the code I worked on this morning. #FPGA

Verilog code showing how Isle detects attempts to access unmapped memory addresses.

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Flux @willflux.bsky.social · 19/07/2026

One courgette on the allotment managed to hide amongst the leaves.

Viking minifig riding a chunky courgette.

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Flux @willflux.bsky.social · 16/07/2026

I try to learn from past hardware, but I have to wonder what Sega were thinking with the Saturn architecture. Just look at the motherboard! I don’t envy game devs starting out with it. www.copetti.org/writings/con...

Labelled motherboard of Sega Saturn showing many processors.

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Flux @willflux.bsky.social · 28/06/2026

Think before you buy that dried fruit. #lego

Legos minifig standing on a bag of Dried Spanish Mini Figs.

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Flux @willflux.bsky.social · 26/06/2026

Goodbye Radio 4 on Long Wave; on air for the last time today! www.bbc.co.uk/reception/wo...

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Flux @willflux.bsky.social · 11/06/2026

A first successful test for hardware scrolling, showing vertical and horizontal wrapping of my latency test image. You can see the four corners of the bitmap meeting in the bottom right of this capture. #FPGA

Verilator/SDL simulation running Isle.Computer hardware. The test bitmap has a single pixel yellow border around the edge. Having scrolled the bitmap canvas, the four corners of the yellow border meet together in the bottom right of the image.

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Flux @willflux.bsky.social · 07/06/2026

🏝️Isle.Computer now supports arbitrary bitmap canvas sizes: github.com/projf/isle/b... Not too exciting on its own, but it makes it much easier to support multiple resolutions and hardware scrolling. #FPGA

256x160 16-colour crocus bitmap scaled up 2x (512x320) and rendered in the top-left corner of a 672x384 Verilator/SDL simulation of Isle Computer. The remainder of the window, not covered by the crocus image, is navy blue.

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Flux @willflux.bsky.social · 05/06/2026

Looking promising. Here the #riscv CPU is updating the text scrolling register. There’s CDC from system to pixel clock domain. #FPGAFriday

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Flux @willflux.bsky.social · 02/06/2026

Well, it works in simulation with one clock domain. But will 🏝️ Isle.Computer hardware registers work on real hardware with two clock domains? 🤔 #FPGA

Isle.Computer Verilator/Simulation window. The window has a very dark green background. Yellow and green text in the window reads:

Isle.Computer
Display: 672x384
Bitmap: 672x384
Text: 84×24

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Flux @willflux.bsky.social · 31/05/2026

Yikes. .io is expensive these days. But I’d be sad to retire projectf.io.

Domain renewal notice for projectf.io - $74.74 for a year.

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Flux @willflux.bsky.social · 21/05/2026

AMD (Xilinx) are no longer supporting Linux in the free version of #Vivado. You need to pay at least $1200/year! www.amd.com/en/products/... This makes no sense to me. This will make it harder for people to learn and get into #FPGA. 🤔

Extract from AMD Vivado feature chart showing the $1200/$1800 version supports Windows and Linux, while the Basic (Free) version only supports Windows.

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Flux @willflux.bsky.social · 07/05/2026

I just voted 🗳️ in the Hastings and East Sussex #elections.

A polling station at a church. There are two signs, one says The Parish Centre and the other Polling Station.

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Flux @willflux.bsky.social · 02/05/2026

Made some time for 🏝️ Isle.Computer today. Getting the graphics registers working across clock domains so the CPU can double buffer, scroll, adjust transparency etc. #FPGA Images show RISC-V CPU reading graphics registers in sim and on #ULX3S.

Verilator/SDL simulation window running Isle on macOS. The window has a dark green background with the following text:

Isle.Computer
Display: 672x384
Bitmap: 672×384
Text: 84×24

ULX3S FPGA dev board (green PCB with chips) connected to monitor. The screen background is dark green with the following text:

Isle.Computer
Display: 1366x768
Bitmap: 672×384
Text: 84×24

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Flux @willflux.bsky.social · 29/04/2026

Just when you thought GPU pricing had lost the ability to shock. A mobile 5070 for £1150! 😮

RTX 5070 12 gigabyte graphics module for Framework 16. Price £1150 inc VAT. $1200 in US.

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Flux @willflux.bsky.social · 26/04/2026

French bram is on another level. #fpga

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Flux @willflux.bsky.social · 16/04/2026

Sometimes the wrong palette turns out right.

16 colour image of crocuses in grass with the wrong palette. The flowers are green and blue while the grass is bright pink, purple, and sand coloured.

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Flux @willflux.bsky.social · 11/04/2026

Verilog error message of the day: "Illegal character in binary constant: 2". Yes, I'm appalled at myself too.

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Flux @willflux.bsky.social · 01/04/2026

The drawing engine refactor was getting chunky, so I merged it. If you want to have a play, there are a few (not enough) details on the 🏝️ Isle.Computer blog: projectf.io/isle/2d-draw... This refactor will allow me to share vram between CPU and drawing engine for the first Isle release. #FPGA

Earthrise 2D drawing test image on widescreen monitor driven by an FPGA dev board over HDMI. A mixture of lines, triangles, and circles in greens and oranges.

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Flux @willflux.bsky.social · 29/03/2026

Adding an enable signal to 🏝️ Isle.Computer drawing engine was more of a pain than I expected, but we're now ready to share vram access with the CPU. On the plus side, this also allows you to slow the action down so you can see the drawing happen. #FPGA #verilog

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Flux @willflux.bsky.social · 27/03/2026

I've just updated 🏝️Isle chapter 6 software. It's exciting to work on big designs and graphics engines, but building a usable computer is about the small things too. #FPGAFriday github.com/projf/isle/t...

* support negative numbers in strd_int
* optimise strd_int, reducing branches in loop from 3 to 1
* reject invalid hex characters in strx_int :;<=>? (U+003A-0x003F)
* add number/string example program software/book/ch06/num_str.s
* rename keyboard include to unicode and change constants UNI_ -> UCS_
* add chapter 6 memory map to README

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Flux @willflux.bsky.social · 20/03/2026

You can find the source code on GitHub (I'm considering moving to Codeberg): github.com/projf/isle Includes everything you need for: * Machdyne Lakritz (Lattice ECP5) * @digilent.bsky.social Nexys Video (Xilinx XC7) * Radiona #ULX3S (ECP5) * Verilator simulator with SDL (Linux/macOS/Windows)

Isle echo program running in Verilator/SDL simulation.

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Flux @willflux.bsky.social · 20/03/2026

Sometimes you need to ship it and call it a night, so I give you 🏝️ Isle.Computer Chapter 6 - Input Output: projectf.io/isle/input-o... Adds input hardware, uart, Isle edition of FemtoRV "Gracilis" RV32IMC CPU, software library in #riscv asm, Verilator/SDL sim improvements... #FPGA

Isle.Computer running on ULX3S FPGA dev board connected to monitor showing number guessing game.

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Flux @willflux.bsky.social · 19/03/2026

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

ULX3S FPGA dev board connected to monitor showing number guessing game.

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Flux @willflux.bsky.social · 19/03/2026

Macintosh memory is so expensive. systemtalk.org/post/macinto...

A Killy Corp memory upgrades advert from 1986. 128 to 512 is $173. 512 to 2 meg is $549.

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Flux @willflux.bsky.social · 18/03/2026

Tired of Teams? Meet Macintosh style from 1985 with VMCO. I wonder if this could be ported to #GlobalTalk? 🤔 systemtalk.org/post/macinto...

Photograph of page from MacUser December 1985: “VMCO is the Visual/Vocal MAUG Conferencing Utility. It’s a communication program that integrates MacinTalk, Apple’s speech synthesis program, and the conferencing (or group meeting) software…”

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Flux @willflux.bsky.social · 05/03/2026

If you enjoy my work on 🏝️ Isle.Computer, FPGAs, and RISC-V, consider sponsoring me: projectf.io/sponsor/ You get early access to source code and blog posts, and I send you a newsletter every month or so. Plus, you help me bring these open-source projects to life. ☺️

A coconut sapling growing on a tropical beach.

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Flux @willflux.bsky.social · 04/03/2026

I've added more software to 🏝️ Isle.Computer; all handwritten in bare-metal #riscv asm.The number guessing game exercises a surprising number of low-level features. Source code (on temp branch): github.com/projf/isle/t...

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Flux @willflux.bsky.social · 02/03/2026

Over the weekend I worked on 🏝️Isle.Computer designs for chapter 6. I've now added the designs to a branch and you can already run the sim on your PC (Linux/Mac/Windows): github.com/projf/isle/t... Please have a quick play and let me know how you get on. 🛝

Verilator/SDL simulation running Isle hardware and software. The screen contents read:

Hello, this is Isle.Computer demoing Unicode read line in RISC-V assembler.
Open source Verilog hardware and bare metal RISC-V assembler. :)
We have block elements in the character ROM.

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Flux @willflux.bsky.social · 01/03/2026

Sometimes Wikipedia gives you more than you dared hope (animated PNG). en.wikipedia.org/wiki/River_c...

An animation of the wolf, goat and cabbage problem crossing a river

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Flux @willflux.bsky.social · 25/02/2026

Linear-feedback shift registers (LFSR) are a classic way to generate pseudorandom numbers. I've written a #riscv asm function to return a random number using my lfsr hardware. This is part of the next instalment of 🏝️ Isle.Computer.

# rand_pseudo - return a pseudorandom number using lfsr
# a0: start of range (unsigned)
# a1: end of range (unsigned)
# return: pseudorandom number
#
rand_pseudo:
li t6, SYS_DEV

# check range is positive: ensure a1 ≥ a0
bleu a0, a1, 0f # skip if already in correct order
mv t0, a0
mv a0, a1
mv a1, t0
0:
# determine range: a2 = a1 - a0 + 1
sub a2, a1, a0
addi a2, a2, 1
beqz a2, 2f # branch if full range (a2 wraps to 0)

# rejection threshold to remove bias
neg t1, a2 # 2^32 - range
remu t1, t1, a2 # threshold = 2^32 % range
1:
# sample lfsr and check threshold
lw t2, LFSR_32(t6)
bltu t2, t1, 1b # reject if bias value (try again)

# create random number in range
remu t2, t2, a2 # divide by range
add a0, t2, a0 # add start of range
ret
2:
# sample raw lfsr output for full range
lw a0, LFSR_32(t6)
ret

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Flux @willflux.bsky.social · 16/02/2026

This Hastings shop wants you to STOP! 🙀 Though I'm now thinking of @gossjam.bsky.social.

Sign in window of shop reads:
!!!STOP!!!
GIVING CATS
!!!TREATS!!!
DONT PUT
HAND
THROUGH
LETTERBOX

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Flux @willflux.bsky.social · 12/02/2026

And a quick lunchtime shot of 🏝️ Isle.Computer running on #ULX3S. Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. 😊

Isle.Computer running on ULX3S dev board connected to computer monitor over HDMI. The text on the monitor reads:
Isle.Computer
Hello, hardware friends.
Demos look better on a dev board :)
Thanks to my sponsors.

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Flux @willflux.bsky.social · 11/02/2026

I'm beavering away on practical input and output with UTF-8 on Isle.Computer. Text is a wonderful thing in its own right and also decidedly handy for debugging. The designs for the next chapter aren't too far away. #FPGA

Verilator/SDL simulation window on macOS reads:
Isle.Computer
Hello, this is a 115200 baud test on Isle Computer.
We also have delete and carriage return.
Next up there's buffered input with a fifo...

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Flux @willflux.bsky.social · 05/02/2026

Unicode UART goodness for 🏝️ Isle #FPGA Computer. SDL key presses to UART via C++, sent to Isle hardware running under Verilator. The Isle #riscv asm software decodes the UTF-8 for display, including ▚ (U+259A). We get Unicode user input in Verilator using same mechanism as physical dev boards. ☺️

Verilator/SDL simulation running on macOS. The window displays the following text in orange on a dark background "▚▚ Hello, World! UTF-8 UART ▚▚".

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Flux @willflux.bsky.social · 03/02/2026

Work on 🏝️ Isle #FPGA computer input chapter continues. Here I’m testing UART with #ULX3S dev board.

ULX3S PCB connected to computer monitor showing “Hello, World! This is an Isle FPGA Computer UART test.”

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Flux @willflux.bsky.social · 30/01/2026

I realised I never posted a video of the advanced asm animation introduced in this chapter.

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