Reposted by Rohan makes ASICs 🛠️Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 17/08/2026And then the fun part started: debugging the actual chip. 😅 Full story bitbangingbytes.substack.com/p/from-taylo...bitbangingbytes.substack.comFrom Taylor Series to Silicon: Building and Debugging a ROM-less CORDICHow we fixed our chip by lying to it 021
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 17/08/2026And then the fun part started: debugging the actual chip. 😅 Full story bitbangingbytes.substack.com/p/from-taylo...bitbangingbytes.substack.comFrom Taylor Series to Silicon: Building and Debugging a ROM-less CORDICHow we fixed our chip by lying to it 021
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 11/08/2026Software has bugs. Silicon has consequences. - An RTL constant that happened to be an input saved the maths. - An SPI phase bit that host could flip saved the link. Both accidents. Both saved the chip. Either Design for testability or don't bother taping out. 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 07/08/2026Do check calibration and silicon characterization report - github.com/rohanverma94...github.comGitHub - rohanverma94/cordic_romless_v1_test_harness: Test harness for ASIC testing of CORDIC design.Test harness for ASIC testing of CORDIC design. Contribute to rohanverma94/cordic_romless_v1_test_harness development by creating an account on GitHub. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 04/08/2026POV: you've blamed the testbench, the tool, the PDK, and the moon. Day 1: "It worked in simulation." Day 2: "It's probably a timing issue." Day 3: "It's probably haunted." Day 4: it was the RTL. 020
Reposted by Rohan makes ASICs 🛠️deeempak.bsky.social @deeempak.bsky.social · 29/07/2026The first tapeout i was a part of feels good to see it working 😁😁 011
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 29/07/2026Coarse measurement with 100 angles on full 0–360° sweep: Mean absolute error 3.53e-4 (1.4 LSB), RMS error 4.09e-4 Fine measurement with 250 angles on full 0–360° sweep: Mean absolute error 4.19e-4 (1.7 LSB), RMS error 5.20e-4 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 29/07/2026We have the silicon. And it's working🎉🍾 ROM-less CORDIC engine hooked up to an SPI master @ 22 MHz. Thanks @tinytapeout.com We pulled it off! Cheers to @aksharvastarpara.bsky.social, Rohan Sundar, @deeempak.bsky.social, Praveen, Devang, Rishik, and Tejas. 221
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 24/07/2026The SCL 1.2µm PDK just dropped on eChipHub, but it's gated to students and professionals in India. verify.echiphub.in 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/06/2026That moment when you get a clean edge transition with a clean clock. xilinx xc2064 was indeed a wonderful device. It was quite tricky to get the bitstream working. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/06/2026Wild part is the config pins (M0, M1, M2, CCLK, DONE) still work the same way as on the Xilinx 7 series chips. I wrote a sketch based on arduino nano to offload the bitstream to XC2064. This blog is genuinely a great motivation to understand how far FPGAs have come - www.righto.com/2020/09/reve...righto.comReverse-engineering the first FPGA chip, the XC2064A Field-Programmable Gate Array (FPGA) can implement arbitrary digital logic, anything from a microprocessor to a video generator or crypt... 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/06/2026Had fun doing bring up for XC2064, the first FPGA ever made with 64 CLBs. Scale is so small that, I was able to use Logic Cell Array editor to manually place and route the design by hand, no automation. 3101
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 13/06/2026sovereign AI was a scam New Internet was a scam Web3 was a scam AGI by 2025 was a scam resistors are real MIM cap is real transistors are real kT/C noise is eternal Kirchhoff never lied to you parasitic capacitance will outlive your startup 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 24/05/2026Why stop at verilog gaming? Everything from sprites, controller and character animation is a state machine in itself. Now imagine putting a whole rasterization pipeline in there. 010
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 03/04/2026So this one guy submitted a very cool entry for @tinytapeout.com's demoscene competition. I really liked the gradient and banner and whole starry sky implemented with LFSR. It's crazy that we can put all of this in one or two tiles. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 26/03/2026cooking an asic for demoscene competition 🤘 @tinytapeout.com 030
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 04/03/2026The real question is that where do you draw the line on democratizing silicon? 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 04/03/2026These are bare dies of the Kintex-7 XC7K325T and its pin-compatible Chinese clone, the JFM7K325T from Fudan Micro. Only difference is that GTX transceivers of JFM7K325T behave differently, so the xilinx pcie core wouldn't work by default. 110
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 02/03/2026sit down mehdi.... sometime back there was a whole online mob by same set of people who tried to attack hindus merely for existing in america. 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 20/02/2026BREAKING TRUMP ANNOUNCES MAGAS WILL BECOME 10% MORE STUPID & BELOW THE AVERAGE IQ. 010
Reposted by Rohan makes ASICs 🛠️Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 21/01/2026Fly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - github.com/aesc-silicon... @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social 083
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 21/01/2026Fly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - github.com/aesc-silicon... @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social 083
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 20/01/2026How well do SP10 probes perform when used with high-frequency oscilloscope measurements? 110
Reposted by Rohan makes ASICs 🛠️Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 15/01/2026welcome to our cordic city!! 011
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 15/01/2026yes! it's from that same blender plugin. 010
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 15/01/2026Yes, that’s a GDSII render. Yes, it’s inside Blender. Yes, it’s our design on TTSKY25A chip. @tinytapeout.com @mattvenn.net @urishaked.bsky.social 251
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 15/01/2026can you post the "GPU running on FPGA"? 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/12/2025....while CSIS sponsers terrorism on Indian soil. 040
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/10/2025Innovation in ZMOS process node led to development of modern CMOS and BiCMOS process node where we have 20 metal layers. For instance, Sky130A 130nm process node have upto 5 metal layers. bsky.app/profile/roha... 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/10/2025Back in the day, NMOS chips used only one metal layer, so designers had to squeeze all the wiring onto a single surface. Metal 1: used for local interconnects, this allowed short and dense wiring. Metal 2: used for global signals like buses, clocks, power. 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/10/2025This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3 μm NMOS process with two interconnect layers. It was one of the first NMOS processes to use separate metal layers for local connections and global signals. 110
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 26/10/2025chinese semiconductor industry is creative for sure. Nice idea for analog tapeout for some day. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 26/10/2025This looks like a matrix. Each one has 128 analog switches. We can do 8x16 analog array with one. So this is actually a analog matrix. 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/10/2025And guess what whole hdl for this is written in both system verilog and chisel/scala. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/10/2025Note that Zve32x extension works only on integers, it needs Zicsr and Zvl32b base profiles to be implemented first. Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously. 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/10/2025Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications. It has been prototyped on a Xilinx Ultrascale Plus FPGA platform. github.com/google-coral... 131
Reposted by Rohan makes ASICs 🛠️Tim 'mithro' Ansell @mith.ro · 30/09/2025Leo Moser and myself will be on @crowdsupply.bsky.social 's Teardown Session talking with @helenleigh.bsky.social about @wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjsyoutu.beTeardown Session 56: wafer.space with Tim AnsellYouTube video by Crowd Supply 1116
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 30/09/2025this ryt? ku-fpg.github.io/software/kan... I'll try this. It's more mature I guess?ku-fpg.github.ioKansas LavaThe Functional Programming Group at the University of Kansas applies and extends functional programming technologies to the diverse areas of building computer systems, high-performance computing, info... 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 30/09/2025We already have chisel for this right? or it lacks on something that only Haskell can provide? 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/09/2025FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda. He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares. www.computerhistory.org/revolution/m... 000
