Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 11/08/2026Software has bugs. Silicon has consequences. - An RTL constant that happened to be an input saved the maths. - An SPI phase bit that host could flip saved the link. Both accidents. Both saved the chip. Either Design for testability or don't bother taping out. 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 04/08/2026POV: you've blamed the testbench, the tool, the PDK, and the moon. Day 1: "It worked in simulation." Day 2: "It's probably a timing issue." Day 3: "It's probably haunted." Day 4: it was the RTL. 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 29/07/2026We have the silicon. And it's working🎉🍾 ROM-less CORDIC engine hooked up to an SPI master @ 22 MHz. Thanks @tinytapeout.com We pulled it off! Cheers to @aksharvastarpara.bsky.social, Rohan Sundar, @deeempak.bsky.social, Praveen, Devang, Rishik, and Tejas. 221
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/06/2026That moment when you get a clean edge transition with a clean clock. xilinx xc2064 was indeed a wonderful device. It was quite tricky to get the bitstream working. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/06/2026Had fun doing bring up for XC2064, the first FPGA ever made with 64 CLBs. Scale is so small that, I was able to use Logic Cell Array editor to manually place and route the design by hand, no automation. 3101
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 13/06/2026sovereign AI was a scam New Internet was a scam Web3 was a scam AGI by 2025 was a scam resistors are real MIM cap is real transistors are real kT/C noise is eternal Kirchhoff never lied to you parasitic capacitance will outlive your startup 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 24/05/2026Why stop at verilog gaming? Everything from sprites, controller and character animation is a state machine in itself. Now imagine putting a whole rasterization pipeline in there. 010
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 03/04/2026So this one guy submitted a very cool entry for @tinytapeout.com's demoscene competition. I really liked the gradient and banner and whole starry sky implemented with LFSR. It's crazy that we can put all of this in one or two tiles. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 26/03/2026cooking an asic for demoscene competition 🤘 @tinytapeout.com 030
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 04/03/2026These are bare dies of the Kintex-7 XC7K325T and its pin-compatible Chinese clone, the JFM7K325T from Fudan Micro. Only difference is that GTX transceivers of JFM7K325T behave differently, so the xilinx pcie core wouldn't work by default. 110
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 21/01/2026Fly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - github.com/aesc-silicon... @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social 083
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 15/01/2026Yes, that’s a GDSII render. Yes, it’s inside Blender. Yes, it’s our design on TTSKY25A chip. @tinytapeout.com @mattvenn.net @urishaked.bsky.social 251
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/10/2025This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3 μm NMOS process with two interconnect layers. It was one of the first NMOS processes to use separate metal layers for local connections and global signals. 110
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 26/10/2025chinese semiconductor industry is creative for sure. Nice idea for analog tapeout for some day. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 26/10/2025This looks like a matrix. Each one has 128 analog switches. We can do 8x16 analog array with one. So this is actually a analog matrix. 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 16/10/2025Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications. It has been prototyped on a Xilinx Ultrascale Plus FPGA platform. github.com/google-coral... 131
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/09/2025FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda. He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares. www.computerhistory.org/revolution/m... 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 06/09/2025Low power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks. Check - t.co/vBGGA2i0uX Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible. 1145
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 10/08/2025SPI-slave device for seven-segment display on TT base board. TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs. 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 07/08/2025LMAO Come for India and you'll get a bloody nose. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 05/08/2025The clock looks so beautiful because it's right from FPGA!! 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 05/08/2025ASICs are cool. FPGAs are ❤️. FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social @tinytapeout.com @mattvenn.net @urishaked.bsky.social 192
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 28/07/2025Evening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 27/07/2025When man craves for aesthetics, he craves for God...and good quality probes. 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 22/07/2025FYI CONFIG_PROGRAMN pin is high, since configuration never really began. When I do ecp_prog.execute() It goes low for a fraction of sec then high back again. And after uploading blinky, I should observe 2.5v on TP5, right ? bsky.app/profile/roha... 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 21/07/2025FPGA brother to @tinytapeout.com ASIC. 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 21/07/2025It looks good. Got the power led. Now trying to get it to work as intended. 110
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 21/07/2025I'm getting this It is not able to read ECP5 ID, now what? ( there is power LED on fpga though) 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 18/07/2025Booted KianV uLinux from Hirosh on TinyTapeout ASIC. 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 14/07/2025Then there is also qspi pmod by Mike and Leo Moser, which I also fabricated. 010
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 14/07/2025I fabricated @rebelmike.bsky.social's design for the Tiny Tapeout demo board and then soldered the FPGA. This was my second time soldering a BGA. Had to visit a nearby university to get the X-ray inspection done. 362
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 11/07/2025this one is little sharp but still not very clear on visuals. 010
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 11/07/2025MPW5 up-close and zoomed-in! @tinytapeout.com @mattvenn.net @urishaked.bsky.social 120
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 08/07/2025My TT06 board arrived! I don't have a design on this but I intend to try RISC-V SoCs on this. @tinytapeout.com @mattvenn.net 074
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 30/01/2025Doing same on axon with help from @aksharvastarpara.bsky.social 020
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 12/01/2025Superscalar, the buzzword we all knew but never explored beyond some books. 100
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 12/01/2025Must read papers for processor design. 110
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 08/01/2025FPGA graphics hit different! 💻✨ #Verilog Build things without knowing C or even von-neuman architecture. 110
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 06/01/2025By the way, there's another excellent book on SoC design coming, hopefully around May or June! 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 06/01/2025This is a VAAMAN board. This board features an RK3399 MPU, an Efinix T120 FPGA w/ 112k logic elements, and a high-speed CPU-FPGA link. I'm going to try their Periplex stack, which utilize this link for custom protocol design without relying on MPU capablities. 130
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 04/01/2025Turns out that mech keyboards don't last. Back to the classic membrane keyboard! 000
Rohan makes ASICs 🛠️ @rohan-devarc.bsky.social · 03/01/2025__cooking xv6-riscv on ecp5__ __Have a nice weekend guys__ 040
