iiinova — where your digital self keeps evolving

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Jan Gray @jangray.bsky.social · 27/08/2025

Congratulations @clairexen.bsky.social: #HotChips / IEEE TCMM 2025 Open Source Hardware Contribution Award

Slide from Hot Chips 2025:
"2025 TCMM Open Source Hardware Contribution Award:
Claire Wolf: In recognition of outstanding contributions to RISC-V —
including BitManip, RVFI, and PicoRV32—and to open-source tools like Yosys and IceStorm. [IEEE Computer Society TCMM / Technical Community on Microprocessors and Microcomputers]"

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 26/07/2025

So if you are currently involved with ISA-level decisions about inclusion of any pext/pdep-like instructions: Please consider including SAG/inverse-SAG with bit-reversal of the goats. No matter which of the two implementation methods you are using: All you need to do is not mask the goat bits.

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 24/07/2025

Here is the code: github.com/clairexen/ed... I can't see any obvious reason why that identity should not extend beyond 8-bit units. But I have not actually tested that hypothesis yet.

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 24/07/2025

I have to make a correction regarding ☝️. I've now implemented the Hilewitz-Lee method as well in my edu-sag repository. And it implements the bit-reflecting-SAG as-is. All you have to do is to remove the '&ci' from the data input, thus it's always more area to implement PEXT than bit-reflecting-SAG.

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 20/06/2025

I wrote a reference implementation for a SAG without bit reflection: github.com/clairexen/ed..., and I wrote a parametric SAG core for any bit width: github.com/clairexen/ed...

github.com

edu-sag/param.v at main · clairexen/edu-sag

Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP - clairexen/edu-sag

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 09/06/2025

To have trans friends is to hold candles in the wind. I can’t say if the storm is fate or man-made. I only know I’m losing light.

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Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙

Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 06/06/2025

Yes, I mean the definition of SAG with the mirroring. The non-mirrored version is way more expensive (and IMO actually less desirable anyway). I just wrote this: github.com/clairexen/ed... I've been meaning to write this code for quite some time...

github.com

GitHub - clairexen/edu-sag: Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP

Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP - clairexen/edu-sag

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 16/01/2025

When I was little I wanted a time machine. Now I have (c)PTSD. Beware what you wish for.

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 13/01/2025

I've just posted a reminder on Twitter, that I am now on bsky. Let's make this a doubly linked list: Just in case you wanna see my old Twitter, that I'm not using anymore, here you go: twitter.com/oe1cxw (it'll forward you to "X" but hell no I won't post an X link for this, or call it my "old X" :P)

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Bruno Levy @brunolevy01.bsky.social · 26/11/2024

... and it has a robust CSG engine, described in arxiv.org/abs/2405.12949 (that just got accepted pending minor revisions)

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Matt Venn @mattvenn.net · 25/11/2024

Introducing the Zero to ASIC analog course! youtu.be/wM4cobfjMMQ Don't miss the Black Friday discounts - join the newsletter for $150 off on Friday: zerotoasiccourse.com/newsletter/ Full course details: zerotoasiccourse.com/analog/

youtu.be

Introducing the Zero to ASIC analog course!

YouTube video by Zero To ASIC Course

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Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙

YosysHQ @yosyshq.com · 26/11/2024

After a summer break, our user group meetings have resumed again! In our last call, Katharina CeesaySeitz from ETH Zürich presented her work to detect microarchitectural information leakage via hardware timing side channels. Watch her talk on our Youtube channel! www.youtube.com/watch?v=Kxp-...

youtube.com

yug8

YouTube video by YosysHQ

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 25/11/2024

Thread for #wordle Wordle 1,255 2/6* ⬜⬜🟩🟨🟩 🟩🟩🟩🟩🟩

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Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙

YosysHQ @yosyshq.com · 18/11/2024

1st post on bluesky!

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Charles Eric LaForest, PhD @handle.invalid · 31/05/2024

I've updated my "rules for ready/valid handshakes" to describe both a control implementation I made heavy use of in the past year, and to add discussion on the synchronization operation which underlies ready/valid handshakes, much like ready/valid handshakes underlie AXI4. fpgacpu.ca/fpga/handsha...

fpgacpu.ca

Rules for Ready/Valid Handshakes

A set of rules for consistent and high-performance designs with ready/valid handshakes, and a discussion of the underlying synchronization mechanism.

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 05/06/2024

Wordle 1,082 3/6* ⬜🟨🟨⬜⬜ 🟨🟩🟩🟨🟩 🟩🟩🟩🟩🟩 ROFL 🤣

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 05/11/2023

I probably spent way too much time fiddling with those functions today.. But I'm quite happy with what I ended up with. ツ

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 27/10/2023

Wow. ChatGPT knows about my transition and my new name, but only if you know about it as well.

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 24/10/2023

When I was working on RISC-V BitManip I was doing inverse xorshift as a benchmark example. This picture makes a lot of sense ;)

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Reposted by Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙

David Buchanan @retr0.id · 19/10/2023

different fields of math are a scam to sell more wikipedia articles. it's all the same math, just rearranged

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Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙 @clairexen.bsky.social · 24/10/2023

Gotta post something here as well I guess.. 😅 so here are some selfies I found on my phone that I kinda like 🦋💜✨ #firstpost

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