iiinova — where your digital self keeps evolving

aki-nyan //nullptr::live @aki.lethalbit.net · 20/09/2026

"I want some yuri… local production for local consumption." I am *wheezing*

『Just repeat after me. Don’t worry—I’ve already learned the general vibe of your Mysterious Beautiful Girl act.』

Uh, can I make one request…?

『Go ahead.』

I want some yuri… local production for local consumption.

Like, super codependent, messy yuri between Kei and her Demonsgear…

『What the hell is wrong with you…』

Too much?

aki-nyan //nullptr::live @aki.lethalbit.net · 12/09/2026

So i'm working on cleaning up my website and porting the Zola stuff from Tera 1 over to Tera 2, and I decided to add a public CV page. I think I nailed the contents, it really highlights my numerous qualifications and prestigious accomplishments if I do say so myself

A screenshot of my website with a page titled "Curriculum Vitae" that has the following body:

Meow Meow Meow Meow Meow

* nya
* nya nya
* NYA!

070

aki-nyan //nullptr::live @aki.lethalbit.net · 12/09/2026

I still think the current channel topic for my IRC channel is peak, no need to ever change it again, so it's been like that for 5 years, lmao

happy cat friends | unofficially the meowiest channel on Libera
set by lethalbit at Sun, 30 May 2021 05:10:22 -0700

060

aki-nyan //nullptr::live @aki.lethalbit.net · 09/09/2026

It's a very big big girl chip :v It's got like an SoC with 2 Cortex A72 cores and 2 Corex R5F cores bolted to a shitload of FPGA fabric and a bunch of super high-speed serial transceivers. Also, i'm sorry the chip is actually 78mm by 78mm not 73, silly me :v

System Logic Cells (K): 18,507
LUTs (K): 8,460
DSP Engines (DSP58): 6,864
Dual-Core Arm® Cortex®-A72
Dual-Core Arm Cortex-R5F
Hardened DDR Memory Controllers: 14
Block RAM (Mb): 239
UltraRAM (Mb): 619
GTYP Transceivers (32.75 Gbps): Up to 128
GTM Transceivers (58G (112G)): 32 (16)
100G Multirate Ethernet MAC: 12
600G Ethernet MAC: 4
PCI Express®: 16 x Gen5 x 4
XPIO (Fabric Facing): Up to 264 DDR-only, 2064 DDR + PL
HDIO: 88
Footprint: 77.5 x 77.5 mm

120

aki-nyan //nullptr::live @aki.lethalbit.net · 09/09/2026

This one *only* has 676 pins, one of the big girl FPGAs has something like 6865...

A photo of the Xilinx VSVB6865 footprint, which only the XCVP1902 has

130

aki-nyan //nullptr::live @aki.lethalbit.net · 06/09/2026

So i'm looking at a Xilinx reference design, just to get some idea of how to best do a fanout, and, they just, have the MTGREF resistor do a whole snake like this, rather than putting it right under the two pads? I mean, it works but, uh, seems less than ideal, IMO....

a screenshot of the bottom corner of a Xilinx Kintex device showing two traces highlighted which snake out and around to a single resistor

260

aki-nyan //nullptr::live @aki.lethalbit.net · 06/09/2026

Mmmm, a clean ERC, good feeling, until I realize I horribly and fundamentally fucked something up and then it's chaos

Screenshot of the KiCad ERC (Electrical Rules Check) window showing 0 Errors, 0 Warnings, and 11 Exclusions

150

aki-nyan //nullptr::live @aki.lethalbit.net · 26/08/2026

I also have a whole mostly up-to-date local bitsavers mirror weighing in at 1.3TiB.... Which i'm tempted to keep, but that can possibly be moved to tape as well, even though I do reference it every so often

A screenshot of the lower right corner of a filelight pie chart showing a 1.3TiB bitsavers archive at `/pool/abyss/Other/bitsavers`

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aki-nyan //nullptr::live @aki.lethalbit.net · 26/08/2026

Yeah, the 1.4TiB of Xilinx installers is not helping, those can happily live on tape or a spare cold HDD.

A screenshot of the upper-right corner of a filelight pie graph showing the path `/pool/abyss/FPGA/Xilinx/Assets/installers` taking up 1.4TiB

110

aki-nyan //nullptr::live @aki.lethalbit.net · 26/08/2026

Cool time to be running out of storage and needing to buy some new disks, ugh.

A screenshot of `dysk` output showing the filesystem `abyss` which is a ZFS pool using 9.4TiB of it's 10TiB capacity, so, just about 90%

260

aki-nyan //nullptr::live @aki.lethalbit.net · 26/08/2026

Yeah, I think rust-analyzer is having a hard time....

$The rust code `for StrDiagnostic<'_> {` with the inlay hint in the lifetime field of `'a: 'a: 'a: 'a:` before the `'_`$

040

aki-nyan //nullptr::live @aki.lethalbit.net · 26/08/2026

So, TIL that VSCode has the `:` fenced emoji short codes for git commit messages because they're parsed as markdown. And *also* that they're expanded even inside of inline code fences (`'s)....

A screenshot of the VSCode git commit flyout showing a commit I did 3 minutes ago, it reads "constraints: Elided `'de` lifetime in `serde::de::Visitor` impl", but the `:de:` inside the code fence is rendering as the German flag

050

aki-nyan //nullptr::live @aki.lethalbit.net · 26/08/2026

match ...match ...match ...match ...

3100

aki-nyan //nullptr::live @aki.lethalbit.net · 24/08/2026

She is trying to help (she is not managing to do so) I love this little gremlin, even if she does want attention right when I'm trying to get work done, such a little bug.

A blurry photo of annie standing over an FPGA dev board with it's lights on and a bunch of cables coming off of it,

Annie is blurry

1192

aki-nyan //nullptr::live @aki.lethalbit.net · 22/08/2026

How you know you're reading the good:tm: documentation :v

A screenshot of a NeoVim editor with the following text:

#
# This material contains trade secrets or otherwise confidential information
# owned by Siemens Industry Software Inc. or its affiliates (collectively, "SISW"),
# or its licensors.
# Access to and use of this information is strictly limited as set forth in the
# Customer's applicable agreements with SISW.

# Unpublished work. Copyright 2024 Siemens
#
# All Rights Reserved.
#
#

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aki-nyan //nullptr::live @aki.lethalbit.net · 21/08/2026

New sticker means I need to find a place to put it, so now tate mode ascari lives on my spectrum analyzer

A photo of the bottom right corner of a Rigol DSA 815 spectrum analyzer with two stickers on it, the one on the left is an FCC notice sticker the one on the right between the two inputs is a tate mode ascari sticker

080

aki-nyan //nullptr::live @aki.lethalbit.net · 17/08/2026

This is what a good email subject looks like people, take notes!

A screenshot of an email line item that reads "Fat Dragon Tail - Lesbian..."

0101

aki-nyan //nullptr::live @aki.lethalbit.net · 14/08/2026

They are just off in their own little corner while the rest of this document is my incomprehensible scribbles. lol

A full screenshot of the Krita document, it's a jumble of many colors and poorly done circles, boxes, lines, and arrows mixed with my unreadable handwriting.

The doodles previously mentioned are near the center-bottom right

040

aki-nyan //nullptr::live @aki.lethalbit.net · 14/08/2026

So I found the krita file I was using to roughly wiggle out the ideas and structure I had for sigcrush, and I forgot I had some little doodles in it. (also ough my handwriting is so bad, I can't read most of the rest of this...)

A screenshot of a Krita canvas with a few doodles on it.

On the left is a poorly done cat face with her paw in front of her mouth done in red.

In the upper right is a purple little microchip with a smiling face on it done in purple, there is a heart in red with blue lines around it above it. These are also all poorly drawn.

On the bottom is a poorly done line graph with the X axis being Cat Ears and the Y axis being LUTs, the chart bounds are done in purple, the axis legends are done in blue.

Inside the chart is a zig-zaggy green line going from the bottom left of the chart to the top right with an arrow on the far right end. written above it in yellow is the text `Nyaaaa~`

150

aki-nyan //nullptr::live @aki.lethalbit.net · 14/08/2026

Was the best I could do, it's very likely a few mm off in quite a few places though, bweh

A photo of a rough board outline in KiCad with a ghost image of the XCKU15P board on in the document

000

aki-nyan //nullptr::live @aki.lethalbit.net · 13/08/2026

Oooh, it might be a 120954-3, which is *NOT* categorized as a backplane connector according to TE, but matches!

A photo from DigiKey showing a connector that looks just like the one on the FPGA board

110

aki-nyan //nullptr::live @aki.lethalbit.net · 13/08/2026

If anyone wants to go connector hunting, here are some rough measurements

A top down photo of the connector in question, showing the four contacts in the housing.

The housing looks to be 14.5mm wide on the outside and the contacts look to be *roughly* 3mm appart?

A rough photo of the connector showing the hight being about 13.5mm to 14mm tall and the contacts about ~6mm high?

A top down photo of the connector showing it to be about 22mm long

110

aki-nyan //nullptr::live @aki.lethalbit.net · 13/08/2026

now, the other modules have test points like this to! but they all seem to be around 30Ω? And the `VS_P` suffix makes me think it's the positive side of the sense feedback, as these have positive and negative side feedback

A snippet of the DP7007G datasheet showing VOUT as pins 19 to 23, +VS as pin 24, PGND as pins 25 to 30, -VS as 31, and VIN as 32 to 36

+VS is labeled as "Positive Voltage Sense" and you should "Connect to the positive point close to the load or VOUT"

-VS is labeled as "Negative Voltage Sense" and you should "Connect to the negative point close to the desired sensing point or PGND"

110

aki-nyan //nullptr::live @aki.lethalbit.net · 13/08/2026

So these are the DC/DC modules all over the board, they're cute! 8-14V in and programmable output at 7A! But, this one specifically has a very *very* low path between it and ground, and I'm not sure why, it's about 3Ω. I don't know exactly what this TP is for, but I suspect it's a feedback/sense

A bel fuse DP7007G DC/DC module with a test point above and below it, the test point below it is labeled V12_VCCO_VS_P

120

aki-nyan //nullptr::live @aki.lethalbit.net · 12/08/2026

BIG! It's an XCKU15P! The current plan of action is to figure out what power input it wants, and then to see if the FPGA is all happy to be poked via JTAG. I hope the whole management section on the right doesn't cause problems, and getting power into it in the first place will be, uh fun.

The front of the FPGA board with a single QSFP28 port then an XCKU15P under a heatsink with DRaM around it, then the rest of the supporting machinery and backplane connector

The back of the board with a whole pile of passives and vias

150

aki-nyan //nullptr::live @aki.lethalbit.net · 11/08/2026

Another pain point is trying to figure out how to do the fan-out for all of the transceivers, It really feels like having to use blind/buried is the only option to get something sane, I know the only real thing to do is try my best, then do sim and see if it holds up.

Another KiCad layout screenshot, this time it's of the top of the FPGA with 18 high speed differential pairs coming in very close to the FPGA

120

aki-nyan //nullptr::live @aki.lethalbit.net · 11/08/2026

Looking at the DDR4 SO-DIMM I still need to route, and still very wiggly about it. I only have 4 viable routing layers, but no blind/buried vias, which means I'm going to have stubs all over the place and can't backdrill... ough...

A screenshot of a KiCad board file with a SO-DIMM slot and an FPGA with a bunch of colorful airwires going between them.

190

aki-nyan //nullptr::live @aki.lethalbit.net · 11/08/2026

for bug reporting instructions, please see your local transbian

the output of the Vermilion help command at the bottom.

There is the red text that reads "For bug reporting instructions, please see:" and then underneath it are two ANSI color flags, next to each other, one is the 5-stripe lesbian flag and the other is the trans flag.

0182

aki-nyan //nullptr::live @aki.lethalbit.net · 07/08/2026

??? I guess? ?????

$00021d18 fn sysCpuCheck() -> u32 00021d18 { 00021d18 let mut result: u32 = vxPvrGet() >> 0x10; 00021d18 00021d40 if result != 3 00021d40 { 00021d48 result = vxPvrGet() >> 0x10; 00021d48 00021d50 if result != 6 00021d50 { 00021d58 result = vxPvrGet() >> 0x10; 00021d58 00021d60 if result != 7 00021d60 { 00021d68 result = vxPvrGet() >> 0x10; 00021d68 00021d70 if result != 8 00021d70 { 00021d78 result = vxPvrGet() >> 0x10; 00021d78 00021d80 if result != 0x81 00021d80 { 00021d90 result = vxPvrGet() >> 0x10; 00021d90 00021d98 if result != 0x8081 00021d98 { 00021da4 let r3_6: *mut c_void = strlen(" 00021da4 A PPC603 VxWorks image cannot run on a PPC604!\n"); 00021dac sysSerialHwInit();$

100

aki-nyan //nullptr::live @aki.lethalbit.net · 07/08/2026

Look at that, 10 PRs, all without the need for any LLM garbage, It's just that easy,

A screenshot of codeberg showing 10 open PRs, all labeled `WIP` for primitive libraries for various FPGAs, there is the Lattice ECP5, machXO2, machXO3L, iCE40, Certus-NX, CertusPro-NX, and CrossLink-NX, and the Xilinx 7-Series, UltraScale/UltraScale+, Zynq 7000, and Zynq UltraScale+ devices

050

aki-nyan //nullptr::live @aki.lethalbit.net · 07/08/2026

got my paws on a brush pen, it is hard to use, lol

A poorly messily drawn cat face in black in on an orange sticky note, with the tip of a brush pen in the bottom left corner

0192

aki-nyan //nullptr::live @aki.lethalbit.net · 04/08/2026

Pending any better place to put them, they shall live on the back of my tablet I guess

The two Aurahack ascari stickers on each corner on the back of the tablet and also there is a secretsaucy and kittenboogers stickers also on the back

010

aki-nyan //nullptr::live @aki.lethalbit.net · 03/08/2026

Huge thank you to the person who basically grabbed everything on Annie's list! Some of it got here already and she's making full use of it being a little baby like always~

Annie mid scratching on her new cardboard scratching post with her butt up and paws together,

Annie on her side mid play with the little feather toy on the side of her new carpeted scratching post

0110