Hi! We build fast verilog simulators using just in time compilation. Our simulator outperforms existing verilog simulators by up to x100. verijit is a project by @cfbolz.bsky.social and Can Joshua Lehmann.
Check out out demo video here: www.
youtube.com/watch?v=PXgUsEjvAOY
youtube.com
Verijit – Up to 100x faster Verilog simulation
YouTube video by verijit