AI may accelerate semiconductor design, but users still need formal proof, semantic continuity, and auditable workflows to trust automation.

Larger packages, finer routing, and embedded functions are pushing advanced substrates toward application-specific designs.

AI agents move deeper into chip design; China doubles down on AI compute and memory; chip supply chains tighten for equipment and critical materials; TSMC partners accelerate; ICs head to space; optic...

Specialization and orchestration are becoming more important as the role of AI agents in chip design widens, but coordination, control, and trust remain challenging

A mixture of expert agentic AI systems can focus on their tasks with or without a commanding general, but challenges remain in drawing boundaries between human and AI effort.

Behind the scenes, advanced equipment control and robotics are enabling higher levels of repeatability, tool uptime, and yield.

Options and workarounds for improving reliability in chips.

Major memory deal; AI Infra Summit news; U.S. chip capacity plans; 2nm & below advances; Huawei's chip offensive; RoT solution for data centers and AI SoCs; Chinese equipment makers gain share; India'...

Models need to be synchronized with what manufacturing actually builds.

Even though the benefits are accepted, a combined hardware/software development flow is hampered by a lot of challenges.

Redundant feeds protect uptime, but they also strand capacity that could support more hardware.

Discrete steps are being merged with others as dimensions shrink into the angstrom range.

Through better manufacturing screening, DFT for systems and fleet monitors, this major scourge on data center hardware is gradually being tamed.

12-inch high-NA EUV masks; Arm's edge AI push; Amkor's expansion; 3D memory; FeRAM startup makes waves; Qualcomm-AWS $60B custom silicon deal; Ayar Labs' scale-up deal; new iPhone chip and format; rog...

Kilowatt-class AI accelerators are forcing engineers to rethink what counts as adequate coverage across workload, thermal behavior, test hardware, and time.

Just because a chip is deemed good doesn't mean it will work as expected.

2D Tunnel FET; in-memory photonic computing; India's $13.4B Semicon 2.0; SEMICON Taiwan; PCIe 6/7 test; MediaTek deal; 300mm Si photonics; InP expansion; $75M to recycle rare earths; GF PDKs; Gain-Cel...

Robots and autonomous vehicles are both edge devices, but a humanoid has wheels as well as fingers. Close interaction with humans raises the stakes.

Part I: Novel integration modules and standard cell configurations.

Can LLMs turn a specification into a set of formal properties that can be used to verify an implementation? The answer is getting closer to being yes, but with caveats.

Thermal drift, stress, electromagnetic coupling, and verification gaps are turning optical integration into a full-system co-design problem rather than a plug-in bandwidth upgrade.

Hot Chips AI HW wave; HBM vs HBC; capacity buildout; Infineon's latest buy; advanced packaging enablers; foundry report; ASIC security threats; IC tariffs; executive changes; Nvidia, Synopsys earnings...

Hot Chips AI HW wave; HBM vs HBC; capacity buildout; Infineon's latest buy; advanced packaging enablers; foundry report; ASIC security threats; IC tariffs; executive changes; Nvidia, Synopsys earnings...

Hot Chips 2026: Thinner dies, more TSV area, thermal dissipation, and limited manufacturing capacity make HBM scaling much more difficult.

Is it better to cram more compute into each rack or rethink the architecture?

Chips are getting bigger, more modular, and much more capable as new innovations mix with existing processes and long-researched projects go mainstream.

Performance advantage may come down to material choices and precise interconnect decisions.

New Micron lab; chip/AI price jump; multi-die monitoring; cryo links for quantum chips; interconnect RC bottleneck; 18A win; CPO roadmap; 2 new CEOs; humanoid readiness gap; Hot Interconnects.

There is no one-size-fits-all — yet.

The next power bottleneck is no longer just inside the accelerator — it is the full conversion path from medium-voltage AC to sub-1V silicon.

No system can be optimized without an understanding of both the hardware and software, and making the right architectural choice requires cooperation.

Lam Research and ASE expansions; data center shifts; CPO system architecture initiative; 2D-transistor interface solution; USENIX HW security; patent suits; image sensors; programmable AI memtransistor; Nvidia's new plan; earnings; Tier IV's L4 auto chip.

As AI clusters push beyond rack-scale limits, optical interconnects and circuit switching are reshaping how data centers scale.

Across the CPO ecosystem, profitability will not happen until standardization occurs.

High-bandwidth memory has become a proving ground for 3D stack testing, DFT, and reliability.

NASA is in the process of bringing terrestrial internet capabilities to astronauts, rovers, and orbiters, which means a network of high-value data will be up for grabs by ransomware actors or rogue na...

SK hynix's $38B new fabs; memory density increases; 2026 chip industry revenue to hit $1.65T; imec metrology roadmap; MIT's self-assembled contacts; new U.S. restrictions; Intel's new training program...

SK hynix's $38B new fabs; memory density increases; 2026 chip industry revenue to hit $1.65T; imec metrology roadmap; MIT's self-assembled contacts; new U.S. restrictions; Intel's new training program...

AI has access to every known security paper and powerful tools, but that's not all bad.

Scaling NoCs across chiplets requires earlier validation of coherency, congestion, thermal effects, and fault behavior.

YouTube video by Semiconductor Engineering

DAC's big buzz; CHIPS Act $; China's immersion DUV; UMC expands; SIA's state of the industry; DRAM shortages; earnings; PCB design credential program; IBM's quantum advantage; AI security alliance; fo...

For compute-intensive applications, clusters of nodes that act as a single computer offer a way to scale performance and provide a workaround for organizations that lack access to leading-edge AI chip...

As packages get larger and thinner, warpage is becoming a process-control problem rather than a simple flatness spec.