Hot Chip 2026解説の第5弾はArmのAGI CPUである。AGI CPUは連載870回でも説明しているが、今回はもう一段踏み込んだ情報が公開された。

The continuation of Freerouting's development depends directly on the financial support of the project. If you feel that Freerouting has helped you, saved you time, or delivered value to your PCB d...

大阪公立大学は5日、2日から発生している大規模なシステム障害について、ランサムウェア（身代金ウイルス）によるサイバー攻撃と判断したと発表した。身代金の要求の有無については「調査中のためコメントできな…

Upgrade your server with the MINISFORUM ESP4B PCIe to 4x NVMe M.2 Expansion Card. It features a PCIe 4.0 x4 host interface, 4x M.2 NVMe SSD slots, compatibility with Intel & AMD platforms, and OCuLink expansion support.

mold 3.0.0 is a new major release of the high-speed linker. As we announced in the 2.42.1 release notes, we have rewritten mold from C++ to Rust, and this is the first release of the Rust version. ...

# 概要 今回もここでしか語れないエピソードも交えつつ、進めていきたいと思います。 前回実施した内容は下記リンクをご覧下さい。ご参考まで。 https://connpass.com/event/367389/ ※管理者の判断により、参加をキャンセルさせていただく場合があります。ご了承下さい。 # 発表枠について 若手発表枠は、30歳以下のためのもので、試験的に導入してみました。是非お気軽にやっていることの発表をして頂ければと思います。発表は6枠用意してありますが、発表希望者多数の場合は一人当たりの発表時間を短くして8枠まで増やす可能性ありです。 ライトニングトークも開催します。...

Improvements Wayland: Added support for passing the text around the cursor. GH-352 Wayland: Added support for content type. GH-355 Wayland: Added support for mouse in the candidate window...

To receive a notification when a new release is available, click on Watch > Custom > Releases at the top. scrcpy v5.0 Changes since v4.1: Add hardware decoding (#7057, #7001, #1894, #1672) Improv...

10月4日、Unity用ツール「VRoid 2 VRC」の販売が開始されました。開発者は、後天性アリス（がそさん）氏。VRoid Studioで作成したVRMモデルを、VRChat向けのアバターへ自動変換するツールです。 […]

ロシア東部シベリアの研究所で危険な感染症の病原体とみられるものが流出し、研究者1人が死亡した。ロシア当局は事案への対応に追われている。

プロゲーミングチーム・FAV gamingが、新たに「女性格ゲーマー部門（Girls Fighting Games）」を設立。第1号選手として、CHINAMIさんの加入を9月30日に発表した。CHINAMIさんは、格ゲーVTuberグループ「りーさるぷらん」に所属する蒼輪ちなみ（そうりん・ちなみ）さんと同一人物。蒼輪ちなみさんとしてのVTuber活動は今後も継続しながら、オフラインの大会やイベントではCHINAMI名義で活動していく。本人も発表にあわせてYouTubeでのライブ配信で、今後の活動...

The security of RSA is generally understood to be based on the complexity of factoring, and key size parameters are extrapolated from the general number field sieve (GNFS). However, this may not accurately represent RSA security in practical scenarios. An under-appreciated 2007 algorithm of Joux, Naccache, and Thomé allows an attacker to forge RSA signatures after temporary access to a raw RSA signing/decryption oracle in time close to the *special* number field sieve (SNFS) without factoring the key. We implement and run this algorithm for 1024-bit RSA. In total, the attack took 1380 CPU core-years over five calendar months, and made $2^{32}$ oracle queries. Most of this time is precomputation; after the precomputation the attacker can forge any signature of choice, offline, in 180 core-years. We carried out our attack using a hardware security module (HSM) as the signing oracle, thus demonstrating the ability to impersonate the HSM through black-box API interactions, without exfiltrating the key. Blind RSA schemes also provide such a signing oracle. Extrapolating our empirical running times to larger key sizes, we conclude that the concrete security of RSA with a signing oracle should be 15 to 30 bits lower than the factoring-based security estimates for the 1024-bit to 4096-bit RSA parameters that are common in practice. Even 4096-bit RSA does not appear to meet a 128-bit security level in this attack model. This highlights a gap in current RSA-type security assumptions, and gives classical cryptanalytic evidence in favor of moving away from RSA entirely during the current post-quantum transition.

OS Images of Phosh's Nightly Builds

最新話:第12話 2026/10/02更新。再生（累計）: 5990。 全話無料。 祭壇ガチャのある世界で。

The coreboot project is pleased to announce the release of coreboot 26.09. In the three months since the 26.06 release, 120 authors (including 29 contributors landing their first patches) merged over 1300 commits across the tree. We thank everyone who wrote code, reviewed patches, tested on hardware, or reported bugs during this cycle. While recent releases have heavily featured new silicon enablement, this cycle focuses on hardening and refining the existing codebase, alongside notable feature work such as shared CFR setup menus, Intel MIPI camera ACPI generation for non-ChromeOS OS stacks, and continued AMD Turin bring-up. A significant amount of work went into teaching the compiler to validate LPC decode windows, replacing opaque audio verb tables with structured alternatives, moving coreboot firmware builds to the C23 standard, and extensively auditing parsers for external data formats. These foundational improvements do not always show up in a boot log, but they are exactly what keeps a long-standing project healthy and reliable. The next coreboot release, 26.12, is planned for the middle of December. ## Significant or interesting changes ### treewide: Input validation and general hardening Several externally supplied formats that coreboot parses received an audit pass this cycle. The EDID parser was updated to reject short EDID buffers (0c2df4db29) and prevent reading extension blocks past the buffer end (e2f1db04e9). It also now checks the extension block length inside parse_cea (d5644158dc) and ignores failed extension blocks (b1bc8c6e71). In the commonlib device tree parsing, we validate FDT header self-consistency (190e6467c8) and header block alignments (61d99ab994). The parser will now reject FDT versions 16 and below (44138ac188) as well as unflattened trees with no root (8eedb4334e). Image rendering and storage also saw improvements. The BMP renderer now validates BMP dimensions and ImageOffset bounds (8589952afa), and validates framebuffer geometry bounds before rendering (6ef8ad909f). For storage, the CBFS walker rejects file headers with a too-small data offset (e95bdb7eee), and the FMAP code validates area offset and size in fmap_locate_area() (00d88bed4e). On the SMM side, the bus walk recursion was modified to prevent cyclic recursion (034f4edca5), and the MP init code will halt the boot on SMM initialization failure (297a51a071). Other hardening includes validating the payload size in TPM2 responses (d7a3dfc1f1) and checking for ramstage heap overflow in crashlog (899a40fc9b). ### lib,intel: DDR5 SPD cache and TPM-backed verification Intel platforms gained DDR5 SPD cache support so DIMM serials and geometry can be reused across boots without re-reading SMBus (143cab8eb9), with follow-up size-check fixes in the common SMBus path (0fb58baf02). Separately, `SPD_CACHE_TPM_HASH` stores a SHA-256 of the SPD cache in TPM NVRAM and invalidates the cache on mismatch, forcing a clean MRC retrain if RW flash was tampered with (03903a857f). Google Ocelot variants began opting into the TPM-hash path (5384dc480a). ### build: The firmware build moves to C23 The coreboot firmware build has officially moved to the -std=gnu23 standard (e9f2a15a05). Mainboard code was subsequently updated to replace _Static_assert with the standard C23 static_assert keyword (88c1fac546). Host tooling briefly followed suit (456d48e69e), but that change was reverted before the release because it broke building on older distro versions (f7249a1e4d), so the host tools keep their existing C11 baseline. ### sb,soc/intel: LPC generic decode ranges are now compiler-checked LPC generic decode ranges are now properly validated. We added an LPC_IO() helper for GENx_DEC values to the common southbridge (7e16e70c55) and SoC (819cd9bec3) LPC code. Invalid LPC_IO() values are now rejected at compile time (4ef247411a), and a new lint check requires using the LPC_IO() macro for gen*_dec fields in device trees (99a6a8518f). ### arch/x86: i8259 and virtual-wire ExtINT setup rework The virtual wire EXTINT setup was improved to enable it only after the i8259 initialisation (afa234c6c8), and ExtINT is now kept masked while initializing the i8259 (64bbfac246). We initialized the i8259 on the remaining PC/AT paths (27aae20c29). Additionally, we added a NO_PCAT_8259 policy to gate PC/AT 8259 setup (bce0c6ad5a) for platforms that lack a PC/AT PIC pair. ### device,mb: Azalia verb tables become readable Audio verb tables received a major cleanup to make them readable. We added support for 4-bit verbs (942000193a) and switched to using weak functions to get azalia codecs (c583b0c4f8). Proper enums were added for the Realtek ALC1150 (11ef0fac53) and ALC662/892/1200 (85707dc6a0) codecs. Many ASRock Z87 and Z97 boards were updated to use these human-readable verb descriptions (1f6fa17e4a). ### drivers,ec,console: Shared CFR menus and runtime serial console Setup-option coverage via CFR expanded substantially this cycle. Lenovo H8/PMH7 boards now get a shared EC firmware menu automatically (2f96e1d90e), and ChromeEC gained the same pattern so every CFR-enabled ChromeEC board picks up a consolidated EC form without per-board copies (9916da47e9). On the chipset side, bd82x6x grew a shared Intel ME status and control menu (6f581f4808), with common north/southbridge options for Arrandale-era parts (ce0b89b178) and shared Hyper-Threading controls (b363cc3237, 4a930e7cf3). The console subsystem can now enable the serial console at runtime (605cba2fd1) and auto-publishes a shared CFR Console form (5d76acd9aa), dropping per-board debug-level wiring (8da7079e50). Asset-tag CFR support was added as a generic driver (ac094eb2b7), and CFR was wired up or enabled by default across LattePanda Mu (c6d3e4ba14), Framework (469001e130), cyan (291951d21c), x201/x230 (f34347d790, dfa075e298), and several edk2-default configs (be50f6d4ca). ### drivers/intel/mipi_camera: ACPI generation for IPU3 camera stacks The MIPI camera driver grew a PMIC SSDT generator (9e108b97b0) and richer ACPI binding support aimed at the Windows/Linux driver stack for IPU3 cameras: `_DEP` (c45d969667), external `_STA` objects (be4ad536b2), reset-once PMIC PowerResources (9160dfa147), graph `_DSD` and GPIO `_DSM` (c74e3c9718), SSDB lane derivation (3598a525ec), and local PRIC alongside INT3472 (cc36de97cc). CIO2 port/`_DSD` emission was scoped into the existing device (3321f6013c), with Skylake CIO2 naming and static-child scanning (2f8349943b, d019cf7fcd). Variants that do not set VARIANT_HAS_CAMERA_ACPI now skip these operations entirely (bca239e90a). Google Poppy variants (atlas, nautilus, soraka) moved from static ASL to the MIPI devicetree path (603c189906, b993b3026f, a3a4d23b2c), Volteer restored VCM `PWREN`-only power (2abba28dab), and an ACPI programming guide was added under Documentation/drivers (e3ec4f1fc0). ### drivers/efi: Capsule-on-disk support and an SMMSTORE cleanup The EFI payload infrastructure gained support for capsule-on-disk (56535e2783), and edk2 payloads are now configured to support it (dc67faf538). The capsule driver rejects invalid memory ranges (bd50f39597) and allows the driver to be called multiple times (db6aeea755). SMMSTORE dropped its v1 protocol support (52fd778a78) and made its block size configurable (01a26951a6). ### soc/amd/turin: Turin PoC matures; first EPYC board lands AMD Turin continued past the skeleton stage. The PoC SoC picked up CPPC support (c21b6f255d), IOAPIC interrupt-routing hooks (9a3ca0c141), FADT and amdfwtool configuration (bfddb4ad78, b53955450c), and ACPI descriptions for CXL and MPDMA devices (d0a055ae78, 858049a7ae). SEV NVRAM was hooked into the PSP directories (a8dba0849e), with matching amdfwtool and EFS work for Genoa/Turin (721453b7ff, 0fd91dc227, f0194c62ba, c14cf399e3). The first board on this path is the GIGABYTE MZ33-AR1, added with PCIe slot/MCIO topology, on-board device config, and BMC BIOS-update packing (0754b3ea38, 32b4cddd27, 737480a0da, a53c63b814). Common AMD FCH paths (AOAC, SMI sleep) were unified alongside this work (80fade0ec4, c8d0d2591a, fb11c51fb7). ### Documentation: AI review policy and AGENTS.md coreboot adopted an explicit policy for AI-assisted code review (b34a744391). The Gerrit Guidelines now describe when and how AI may be used on patches, and a top-level `AGENTS.md` encodes the same rules for coding agents: comments must be marked `[AI-generated]`, may only raise new top-level issues (never replies to humans), must not set review flags or drive Gerrit actions, and must follow the project coding style. ## Additional coreboot changes * util/cbfstool: FMD gained an `EXT` flag so CBFS regions can be extended onto alternate storage as `ECBFS_<name>` siblings (a80a718fd9), and fmaptool enumerates those extended regions for cbfstool (db23ba0439). * soc/qualcomm/calypso: Add Calypso RPMh RSC driver (f9617dba37), display subsystem initialization (74410e2a00), and TSENS controllers and thermal zones (e00170ceca). * soc/mediatek/mt8196: Enable EOSC hardware calibration for RTC accuracy (beb40bd594) and break unclocked CBUSY deadlock during MT6685 RTC init (f7c6229c61). * soc/amd: Add BOCO (Bus Off Chip Off) support (90157e8977). * soc/amd/common/block/pci: Add PCIe hotplug support (44f4416b63). * soc/amd/common/block/psp: Add SMM A/B recovery support (0c62b9d21e). * util/amdfwtool: Add multi-PSP support (56fee2ba34) and support for SEV NVRAM (c14cf399e3). * soc/intel/pantherlake: Add configurable TDP support (f57c27b496) and dynamically configure DDR5 memory controller topology (ade6bd7e87). * soc/intel/novalake: Enable coreboot native logo rendering (1f8931aceb) and add TDC, power limits, and power state thresholds (538e724405). * mb/starlabs: Share identical mainboard sources (8dcd09d131) and move shared settings to common files (c2d000ba36). * ec/starlabs/merlin: Generate battery ACPI with acpigen (9810f4a5ef) and generate sleep hooks with acpigen (3c77e34b52). * ec/lenovo/h8: Add keyboard backlight hardware detection (30b8105b0b) and ACPI method _BIX (493593a1b8). * nb/intel/pineview: Add DDR2 UDIMM Vref margining (c96952c3e4) and add libgfxinit support (9c6cb93982). * drivers/wifi: Support Selectively Wi-Fi Bands (3e81074243) and add DSM function 8 ‘Device for Indoor Use Only’ support (61394c0a43). * mb/framework: Enable vboot on all boards (26450cca94), unify EC code across mainboards (4c9e99d07d), and add thermal zones (3449b5e01a). * mb/lattepanda/mu: Split into baseboard (SOM) and lite carrier variant (6bb3ad5902). * mb/sapphire/rave2: Add Rave2 mainboard (41f44c3a35) and add PCIe/DDI topology and enable NVMe/WiFi/OcuLink (8e3ba74abe). * drivers/efi,drivers/smmstore: Reject overflowing variable entries (fae8549751) and validate raw block ranges (4c665df7c3). * util/attribution: Add a build-time third-party attribution file (86263d604c). The list is derived from the enabled Kconfig options and stored in CBFS, so it reflects what is actually in a given image. CrabEFI was added to the list (ebf341c51e). * ec/google/chromeec: Power off on a lid-closed boot (7d288631f6) and expose the behaviour through CFR (04a4067e76). * nb/intel,soc/intel: Replace _Static_assert with the C23 static_assert keyword (841b696b45, a88e41343b). * mb/starlabs: Use firmware CM on Alder Lake and Raptor Lake (fd414c8765) and on Tiger Lake StarBooks (6b3f19169b), with soc/intel/common/block/usb4 allowing boards to override the CM default (8a001a0b5a). * commonlib/cfr: Add a LOCK_AT_BOOT option flag for setup-only writes (af717b4e43). * lib/bootmode,libpayload: Add a boot_reason API and coreboot table record (6975e77994), and google/chromeos: Set the boot reason on a watchdog reset (65630f7f9b). ## Changes to external resources ### Toolchain updates * Upgrade binutils from version 2.45.1 to 2.46.1 (6372edd871) * Upgrade LLVM from version 21.1.8 to 22.1.8 (30870ce128) * Upgrade NASM from version 3.01 to 3.02 (c165edb4ce) * Upgrade CMake from version 4.0.3 to 4.3.4 (560771f617) * Upgrade MPC from version 1.3.1 to 1.4.1 (56fc96dcac) * Add Cortex-R and Cortex-M multilib support to crossgcc (54bcc595c0) ### Git submodule pointers * arm-trusted-firmware: Update from commit id 9109143417 to b5eaba47ef * blobs: Update from commit id 4a8de0324e to 6f42f0f39b * fsp: Update from commit id ca4f8b702d to 98426bfd95 * intel-microcode: Update from commit id 98f8d817ca to 927e65c8d5 * libgfxinit: Update from commit id 7e08e5d280 to 6e74c70313 * libhwbase: Update from commit id 5bd7c1101c to 61f7287f18 ### External payloads * payloads/external/CrabEFI: Add CrabEFI payload support (ff34dafa38). CrabEFI is a UEFI implementation written in Rust. * payload/grub2: Update GRUB2 to 2.14 (bcb8f01241). * payloads/edk2: Configure capsule-on-disk support (dc67faf538) and bump the MrChromebox default revision to 26.09.1 (cd03ec93ad). * payloads/SeaBIOS: Select CONFIG_QEMU_HARDWARE for emulated boards (27595ffcaf). * libpayload: Parse soc_id from coreboot tables (6b028355f7) and recreate MSC disk if geometry changes (0e4ed28002). ## Platform Updates ### Added mainboards: * Acer TravelMate P633-M * Acer TravelMate P633-V * Apple iMac4,1 * ASRock Fatal1ty Z97X Killer * ASRock Z97 Anniversary * ASUS B85M-E * ASUS Maximus VI GENE * ASUS Maximus VII GENE * ASUS Maximus VII HERO * Framework Laptop 12 (13th Gen Intel Core) * GIGABYTE MZ33-AR1 * Google Aneto * Google Annite * Google Hekla * Google Meru * Google Pic * Intel NUC D33217GKE * LattePanda Mu with DFR1141 full eval carrier * LattePanda Mu with DFR1142 lite carrier * Lenovo ThinkPad X380 Yoga * Lenovo ThinkStation P320 * MSI PRO B760-P WIFI DDR4 (MS-7D98) * NVIDIA Porg (Jetson Nano) * Qotom Q535G6 * Sapphire Rave2 (Faegan) * Siemens FA ASL ## Statistics from the 26.06 to the 26.09 release * Total Commits: 1324 * Average Commits per day: 13.87 * Total lines added: 114775 * Average lines added per commit: 86.69 * Number of patches adding more than 100 lines: 148 * Average lines added per small commit: 40.48 * Total lines removed: 27811 * Average lines removed per commit: 21.01 * Total difference between added and removed: 86964 * Total authors: 120 * New authors: 29 ## coreboot Links and Contact Information * Main Web site: https://www.coreboot.org * Downloads: https://coreboot.org/downloads.html * Source control: https://review.coreboot.org * Documentation: https://doc.coreboot.org * Issue tracker: https://ticket.coreboot.org/projects/coreboot * Donations: https://coreboot.org/donate.html

Check end-of-life, release policy and support schedule for Google Pixel.

Aiming for a 10 year life-cycle for smartphones

レグザ、評論家・本田雅一氏宅への100V型RGB Mini LEDテレビ搬入に密着ロケ。第3回は大型クレーンが登場

最新話:第5話 2026/10/02更新。再生（累計）: 94695。 全話無料。 『ニセモノの錬金術師』の杉浦次郎、最新作！ ガチャで、王となれ。 『思うまま 欲望のまま 好きなように生きなさい』 異世界に転生した元フリ…

IPP-Everywhere service on Android/iOS. Contribute to tmyt/imprima development by creating an account on GitHub.

Inline int math up to 8.8x faster + protocols on PHP interfaces + 16 new core fns + sharper errors and lint JSON 🎉 Added Language: defmulti takes Clojure's signature, (defmulti name docstring? att...