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InstLatX64 @instlatx64.bsky.social · 29/09/2026

Given the unique CPUID family (400Fxx), the distinct #PantherCove codename, and #Intel's insistence on distinguishing between server and client cores, I would be surprised if #DiamondRapids did not feature 8x256-bit FPU ports for #AMX, additional FMA and permutation EUs

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InstLatX64 @instlatx64.bsky.social · 28/09/2026

Of course this means also that the desktop #NovaLake 300F1x and mobile #NovaLakeL 300F3x has +50% peak vector performance advantage over the dual-512b-issue #SkyLakeX, #IceLakeX, #SapphireRapids, #EmeraldRapids, #GraniteRapids #AVX512 #AVX10_1 #AVX10_2

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InstLatX64 @instlatx64.bsky.social · 27/09/2026

This #AVX512 implementation suggests that the 6 FPU port in #CoyoteCove delivers 6x256b / 3x512b peak FP performance, which is +50% compared to single-chip mobile #AMD #Zen6 #Medusa (4x256b) and -25% compared to desktop #Zen6 #OlympicRidge (4x512b). #Intel perf + #NovaLake: bsky.app/profile/inst...

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InstLatX64 @instlatx64.bsky.social · 25/09/2026

#Intel released the 93rd edition of the Software Developer’s Manuals with fixes and clarifications: All-in-One: cdrdv2-public.intel.com/929349/32546... Changes v085: cdrdv2-public.intel.com/929348/25204...

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InstLatX64 @instlatx64.bsky.social · 19/09/2026

#AMD released the "AMD EPYC SERVER CPU ARCHITECTURE AND PERFORMANCE OVERVIEW" White Paper: www.amd.com/content/dam/... #Zen6 #Zen6c #AVX512 #x86EAG #EAG #ACE

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InstLatX64 @instlatx64.bsky.social · 14/09/2026

#Intel SDM on web: intel.github.io/SDM/ github.com/Intel/SDM

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InstLatX64 @instlatx64.bsky.social · 13/09/2026

Deobfuscated #Intel #LionCove block diagram reveals further #AVX512 implementation details. According to PMCs, V0 = V1 and V2 = V3 pipes are almost(*) completely identical. This hints that 512b zmm operands are executed in V0+V1, V2+V3 pairs. #CougarCove #CoyoteCove

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InstLatX64 @instlatx64.bsky.social · 10/09/2026

#Intel #BartlettLake CPUID D067x, B067x, B06Fx in coreboot: review.coreboot.org/c/coreboot/+...

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InstLatX64 @instlatx64.bsky.social · 08/09/2026

It seems #AMD #Zen6 #Verano uses SB1 socket: www.dynatron.co/product-page... www.amd.com/en/search/si... #LPDDR5X #SOCAMM2

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InstLatX64 @instlatx64.bsky.social · 06/09/2026

#Intel Trusted Computing Base Recovery (TCB-R) list for IPU 26.3: github.com/intel/Intel-... #TCB

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InstLatX64 @instlatx64.bsky.social · 06/09/2026

#AMD refreshed the "Versioned Chip Endorsement Key (VCEK) Certificate and KDS Interface Specification" 57230 to 1.05 pdf docs.amd.com/v/u/en-US/57...

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InstLatX64 @instlatx64.bsky.social · 01/09/2026

#Intel Platform Update 2026.3 with hybrid info, #GraniteRapids CPUID A06D1 workstation, #ClearwaterForest CPUID D06D1: github.com/intel/Intel-...

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InstLatX64 @instlatx64.bsky.social · 30/08/2026

Great article with #Intel die shots: - #PantherLake (4P+8E+4LPE, #CougarCove) - #WildcatLake (2P+4LPE) - #ClearwaterForest (24c #Darkmont) - #GraniteRapids (44c #RedwoodCove) - #SierraForest (152c #Crestmont) hardwareand.co/dossiers/cpu...

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InstLatX64 @instlatx64.bsky.social · 28/08/2026

#AMD refreshed the "SEV-TIO Firmware Interface Specification" to 0.92: docs.amd.com/v/u/en-US/58...

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InstLatX64 @instlatx64.bsky.social · 28/08/2026

The Queen's Gambit is a very useful series, after which it is much easier to explain what I am doing when it seems like I am not doing anything. www.imdb.com/title/tt1004...

imdb.com

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InstLatX64 @instlatx64.bsky.social · 28/08/2026

#AMD refreshed the "SEV Secure Nested Paging Firmware ABI Specification" to v1.59: docs.amd.com/v/u/en-US/56... #SEV

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InstLatX64 @instlatx64.bsky.social · 26/08/2026

#Intel released the HotChips 2026 conference #CrescentIsland presentation: cdrdv2-public.intel.com/926893/Cresc...

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InstLatX64 @instlatx64.bsky.social · 26/08/2026

#Intel released the HotChips 2026 conference #DiamondRapids presentation: cdrdv2-public.intel.com/926846/diamo... #APX #AMX #AVX10 #PantherCove

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InstLatX64 @instlatx64.bsky.social · 26/08/2026

#Intel refreshed the Advanced Performance Extensions (#Intel #APX) Architecture Specification to 9.0: cdrdv2-public.intel.com/926860/35582... #APX #DiamondRapids #NovaLake #PantherCove #CoyoteCove #ArcticWolf

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InstLatX64 @instlatx64.bsky.social · 26/08/2026

#Intel refreshed the "Intel® Trust Domain CPU Architectural Extensions" 343754 pdf to 3.0: cdrdv2-public.intel.com/733582/34375...

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InstLatX64 @instlatx64.bsky.social · 24/08/2026

Good to see that VS18.9 can now disassemble #APX code #VisualStudio2026

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InstLatX64 @instlatx64.bsky.social · 23/08/2026

How safe is it to assume that if #APX is supported, then #SERIALIZE is too? #Intel #AMD #Zen7 #Zen8

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InstLatX64 @instlatx64.bsky.social · 19/08/2026

The x86 Ecosystem Advisory Group refreshed the #ACE (AI Compute Extensions) specification v1.16.2: x86ecosystem.org/wp-content/u... #EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX

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InstLatX64 @instlatx64.bsky.social · 19/08/2026

I converted the #AMD #Zen6c #Monarch CCD configurations to a more conventional 4x8 layout. I still find it hard to believe that a 32-core chip made with a brand new process doesn't have redundant cores.

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InstLatX64 @instlatx64.bsky.social · 19/08/2026

Interesting post from the Linux kernel list: According to Christian Ludloff (sandpile.org), neither #AMX_TF32 nor #AMX_TRANSPOSE are completely dead. lore.kernel.org/lkml/CAKSQd8...

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InstLatX64 @instlatx64.bsky.social · 16/08/2026

There are already two working #NovaLake CPUID 300F15 among the #Intel test machines: - 24c/24t 3400 MHz [1] - 28c/28t 3200 MHz [2] #CoyoteCove #ArcticWolf #AVX512 #APX enabled [1]: intel-gfx-ci.01.org/tree/drm-xe-... [2]: intel-gfx-ci.01.org/tree/drm-xe-...

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InstLatX64 @instlatx64.bsky.social · 04/08/2026

#Intel released the SDE 10.13.1 (Software Development Emulator) with x86 EAG #ACE (Al Compute Extensions) support: www.intel.com/content/www/... #NovaLake #DiamondRapids #APX #AVX10_2

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InstLatX64 @instlatx64.bsky.social · 02/08/2026

#AMD [1]: - #Zen8 EPYC: Ravenna - #Zen7 EPYC: -- for AI host Ferrara -- for Agentic Sandbox Fidenza - #Zen6 [2], [3]: -- desktop #OlympicRidge B80F80 #AM5 -- mobile #Medusa1 B80F00 AM5/FP10 -- mobile #Medusa2 BE0F00 #FP10 #Intel - #GriffinCove for RZL [4] - #CopperShark [5] - #ThunderHawk [6] 1/3

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InstLatX64 @instlatx64.bsky.social · 02/08/2026

docs.amd.com has now officially revealed that - #Medusa1 is FP10/AM5 - #Medusa2 is FP10 - #OlympicRidge is AM5 #Zen6 #Zen6c docs.amd.com/search/all?c...

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InstLatX64 @instlatx64.bsky.social · 01/08/2026

It's really hard to let go of this 3x11 #Zen6c #Monarch CCD configuration idea, because it simply explains the unusual number of cores in CCDs by disabling rows and columns. Okay, that's not great for L3 latency, but I think something similar is needed for the risk of the brand new TSMC N2 process.

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InstLatX64 @instlatx64.bsky.social · 01/08/2026

#AMD refreshed the "Smart Data Cache Injection (SDCI)" White Paper 58725 to v1.05: docs.amd.com/v/u/en-US/58...

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InstLatX64 @instlatx64.bsky.social · 01/08/2026

#AMD released the "#CDNA5 Instruction Set Architecture Reference Guide" pdf: www.amd.com/content/dam/...

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InstLatX64 @instlatx64.bsky.social · 31/07/2026

Unfortunately, the Perfmon counters of the #Intel #NovaLake INT cluster inherited the grouped nature from the older *Coves with a central scheduler, so the number of ports used here is unknown (except for the 3 JEUs).

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InstLatX64 @instlatx64.bsky.social · 31/07/2026

A new feature was mentioned for #Intel #CoralRapids on the Linux kernel mailing list: APIC timer virtualization lore.kernel.org/lkml/amnPFlS...

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InstLatX64 @instlatx64.bsky.social · 31/07/2026

#AMD -- desktop #OlympicRidge CPUID is B80F80 -- mobile #Medusa2 CPUID is BE0F00 lore.kernel.org/platform-dri...

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InstLatX64 @instlatx64.bsky.social · 31/07/2026

#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 1-5" 40332 to 4.10, all-in-one: Vol1 24592-Rev. 3.25-May 2026 Vol2 24593-Rev. 3.45-Jul 2026 Vol3 24594-Rev. 3.38-Jul 2026 Vol4 26568-Rev. 3.27-Jul 2026 Vol5 26569-Rev. 3.16-Nov 2021 docs.amd.com/v/u/en-US/40...

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InstLatX64 @instlatx64.bsky.social · 29/07/2026

InstLatX64 refresh: #Intel: - 2C+4c #Core 7 350, Core 5 320 #WildcatLake D0651 CPUID dump GitHub: github.com/InstLatx64/I...

github.com

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InstLatX64 @instlatx64.bsky.social · 23/07/2026

Until the 84-core #AMD #Sorano #EPYC 8635P came to mind (12 CCD x 7-core), this 176-core (8 CCD x 22-core) #Zen6c seemed completely incomprehensible without a 3rd CCD type. But supposing 11x3 core within the #Monarch CCD makes this a yield optimization. blogs.microsoft.com/blog/2026/07...

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InstLatX64 @instlatx64.bsky.social · 16/07/2026

#Intel XED got #ACE (AI Compute Extensions) of x86 Ecosystem Advisory Group support: github.com/intelxed/xed... #ACE specification: x86ecosystem.org/wp-content/u... #ACE1 #AVX10_V2_AUX

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InstLatX64 @instlatx64.bsky.social · 14/07/2026

CPUID.1Ah.EAX: 20000000: #Tremont 20000001: #Gracemont 20000002: #Crestmont 20000003: #Skymont 20000004: #Darkmont 20000005: #ArcticWolf 40000000: #SunnyCove 40000001: #GoldenCove 40000002: #RedwoodCove 40000003: #LionCove 40000004: #CougarCove 40000005: #CoyoteCove GitHub github.com/intel/perfmo...

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InstLatX64 @instlatx64.bsky.social · 14/07/2026

#Intel perf tool got #NovaLake CPUID 300F10 300F30 support: According to this commit, while the #ArcticWolf config is quite similar to #Skymont / #Darkmont (8 INT+4 FP, FP probably 128b->256b), the #CoyoteCove FP has increased to 6 ports from 4 in #LionCove / #CougarCove. github.com/intel/perfmo...

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InstLatX64 @instlatx64.bsky.social · 11/07/2026

Another interesting GCC patch: disabling the memory-form of NDD #Intel #APX instructions. #DiamondRapids is not mentioned, perhaps this is an #ArcticWolf related issue? i386: Add tuning to disable memory-form NDD gcc.gnu.org/git/?p=gcc.g...

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InstLatX64 @instlatx64.bsky.social · 08/07/2026

#AMD refreshed the "AMD64 Flexible Return and Event Delivery (FRED) Virtualization" 69191 to v1.10 pdf: docs.amd.com/v/u/en-US/69... #FRED #Zen6 #Venice #Verano

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InstLatX64 @instlatx64.bsky.social · 06/07/2026

An interesting #APX GCC patch: i386: Disable SETcc.ZU generation on DMR/NVL via tune flag gcc.gnu.org/git/?p=gcc.g... Strange, isn't a 6 byte EVEX better than a 2/3/4 byte XOR + 3/4 byte SETcc? #DiamondRapids #NovaLake #PantherCove

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InstLatX64 @instlatx64.bsky.social · 01/07/2026

#AMD #Zen6LP is a collage CPU: ISA: #Zen6 uArch: #Zen5 FPU: #Zen4 (256b) L2: #Zen3 (512KB) L3: #Zen2/#Mendocino (1MB/core) 1/2

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InstLatX64 @instlatx64.bsky.social · 01/07/2026

According to this Linux kernel patch, the #AMD LP-core is clearly marked in the CPUID: CPUID.80000026h.EBX[31:28]=2 #Zen6LP lore.kernel.org/linux-acpi/2...

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