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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Yousef Sadegheih, Dorit Merhof, Muhammad Usman: DEX: Digit-Level Early Exit for Energy-Efficient MSDF Neural Network Inference arxiv.org/abs/2610.11748 arxiv.org/pdf/2610.11748 arxiv.org/html/2610.11748

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Minghan Jiang, Jiayi Wang, Shuaiting Li, Haibin Shen, Kejie Huang: DynaTE: Accelerating Diffusion LLMs via Dynamic Token Execution arxiv.org/abs/2610.11284 arxiv.org/pdf/2610.11284 arxiv.org/html/2610.11284

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Youngmin Oh, Jihwan Won, Yuntae Park, Bosun Hwang, Suwan Kim: ATLAS: Adaptive TDA-guided Landscape-Aware Transistor Sizing arxiv.org/abs/2610.10985 arxiv.org/pdf/2610.10985 arxiv.org/html/2610.10985

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Harun Bayraktar, John Gunnels, Peter Caday: The Missing Fourth Term for the Emulation Tensor Memory Equilibrium (TME) Model: The Residue Deconstruction Cost arxiv.org/abs/2610.10924 arxiv.org/pdf/2610.10924 arxiv.org/html/2610.10924

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Awani Khodkumbhe, Yunfei Feng, Raj Rangarajan, Kevin Wang, Kamal Sahota: RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design arxiv.org/abs/2610.10858 arxiv.org/pdf/2610.10858 arxiv.org/html/2610.10858

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Hao Zheng, Jaime Rafael Imperial, Bardia Nadimi, Xiangfei Kong: A Survey on LLM-Integrated Hardware Design Verification arxiv.org/abs/2610.10580 arxiv.org/pdf/2610.10580 arxiv.org/html/2610.10580

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Aslrousta, Mhapsekar, Asher, Ghanbari, Kalyanapu, Ajorpaz: CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies arxiv.org/abs/2610.10579 arxiv.org/pdf/2610.10579 arxiv.org/html/2610.10579

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

Pei Yu Wong, Thien Tran, Hudyjaya Siswoyo Jo, Jonathan Kua: A Modular Event-Driven Software Architecture for Open-Source Industrial IoT Edge Gateways arxiv.org/abs/2610.10544 arxiv.org/pdf/2610.10544 arxiv.org/html/2610.10544

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 09/10/2026

[2026-10-09 Fri (UTC), 8 new articles found for csAR Hardware Architecture]

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 08/10/2026

Lennart Van Hirtum, David Volz, Andreas Koch, Christian Plessl: SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS arxiv.org/abs/2610.10403 arxiv.org/pdf/2610.10403 arxiv.org/html/2610.10403

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 08/10/2026

Keren Zhu, Yu Deng, Xiaoyu Hao, Liwen Jiang, Zijian Jiang, Cunqing Lan, Boxiang Song, Pujun Su, Yaojia Wang: When Algorithmic Exploration Becomes Cheap: A Case Study of Agentic Research in EDA arxiv.org/abs/2610.10129 arxiv.org/pdf/2610.10129 arxiv.org/html/2610.10129

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 08/10/2026

Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi: ReSAFT: An Efficient Stuck-at Fault-Tolerant Scheme for ReRAM-based Process-in-Memory Accelerators arxiv.org/abs/2610.09999 arxiv.org/pdf/2610.09999 arxiv.org/html/2610.09999

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 08/10/2026

Xiangfeng Sun, Ceyu Xu, Chen Bai, Yuan Xie: BenchmarkAnything: Agent-Driven Construction of Simulator-Ready Microarchitecture Benchmarks arxiv.org/abs/2610.09447 arxiv.org/pdf/2610.09447 arxiv.org/html/2610.09447

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 08/10/2026

Jun Zhang, Weizhi Bian, Hao Zhang: An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC arxiv.org/abs/2610.09292 arxiv.org/pdf/2610.09292 arxiv.org/html/2610.09292

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 08/10/2026

Mahbod Afarin, Tsung-Han Lu, Tajana Rosing: Compiling Semi-Ring Dynamic Programming to Tier-Aware 3D-DRAM Processing-in-Memory arxiv.org/abs/2610.09156 arxiv.org/pdf/2610.09156 arxiv.org/html/2610.09156

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 08/10/2026

[2026-10-08 Thu (UTC), 6 new articles found for csAR Hardware Architecture]

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Ajay Kumar M, Vishnu PS, Yike Li, Shreejith Shanker, Dimitrios S. Nikolopoulos, Bo Ji, Hans Vandierendonck, Deepu John: A Framework for Accelerating Transformer Inference on RISC-V for Edge AI arxiv.org/abs/2610.08688 arxiv.org/pdf/2610.08688 arxiv.org/html/2610.08688

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Jingbo Jiang, Xizi Chen, Jian Peng, Wei Zhang: X-OPM: Explainable Automatic Digital On-Chip Power Modeling for Enhanced Robustness arxiv.org/abs/2610.08502 arxiv.org/pdf/2610.08502 arxiv.org/html/2610.08502

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara, Rahul Bera, Onur Mutlu: Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas arxiv.org/abs/2610.08483 arxiv.org/pdf/2610.08483 arxiv.org/html/2610.08483

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Jaehoon Yang, Jeongmin Lee, Haneul Park, Seung Yul Lee, Nam Sung Kim, Jae W. Lee: Lachesis: Lifetime-Aware KV Cache Placement for Agent Serving across HBM and High-Bandwidth Flash arxiv.org/abs/2610.08378 arxiv.org/pdf/2610.08378 arxiv.org/html/2610.08378

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Zou Qingyun, Bin Gao, Zhuobin Huang, Weng-Fai Wong, Tulika Mitra, Bingsheng He: ECO: Energy-Oriented Configuration Optimization for Attention FFN Disaggregated LLM Serving arxiv.org/abs/2610.08373 arxiv.org/pdf/2610.08373 arxiv.org/html/2610.08373

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Maria Pantazi-Kypraiou, George Goudroumanis, George Floros, Anuj Pathania, George Stamoulis: On the Impact of Degradation-Balanced Scheduling in Manycore Systems arxiv.org/abs/2610.08190 arxiv.org/pdf/2610.08190 arxiv.org/html/2610.08190

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Alexander Kusnezoff, Jo\~ao Paulo C. de Lima, Jeronimo Castrillon, Asif Ali Khan: A gem5-based Simulation Framework for Computing-in-DRAM arxiv.org/abs/2610.08186 arxiv.org/pdf/2610.08186 arxiv.org/html/2610.08186

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Samira Mirbagher-Ajorpaz, Elba Garza, Gilles Pokam, Daniel A. Jim\'enez: CHiRP: Control-Flow History Reuse Prediction arxiv.org/abs/2610.07685 arxiv.org/pdf/2610.07685 arxiv.org/html/2610.07685

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Mhapsekar, Aslrousta, Bhayana, Contreras, Ghanbari, Goodman, Andriiko, Ajorpaz: CACHEFORGE: LLM-Guided End-to-End Generative Cache Replacement Policy for Performance and Hardware Efficiency arxiv.org/abs/2610.07668 arxiv.org/pdf/2610.07668 arxiv.org/html/2610.07668

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Boxiang Song, Keren Zhu: Beyond No-Good Benders Cuts: Exact Realizability for Discretely Tunable Clock Trees arxiv.org/abs/2610.07600 arxiv.org/pdf/2610.07600 arxiv.org/html/2610.07600

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Guo, Wei, Duan, Shan, Morris, He, Li, Chen: A Shape-Adaptive Architecture with Disaggregated Quantization for Efficient LLM Serving arxiv.org/abs/2610.07443 arxiv.org/pdf/2610.07443 arxiv.org/html/2610.07443

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Phillip Pramberger, Athanasios Tziouvaras, Shreejith Shanker, George Floros: A Pipelined FPGA Architecture for Banded Sparse Matrix Dense Matrix Multiplication in Longformer arxiv.org/abs/2610.07301 arxiv.org/pdf/2610.07301 arxiv.org/html/2610.07301

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Yarramneni, Selvam, Haensch, Raghunathan: Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs arxiv.org/abs/2610.07191 arxiv.org/pdf/2610.07191 arxiv.org/html/2610.07191

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Abbas Raza Ali, Muhammad Ajmal Siddiqui, Moona Zahid: Evaluating Inference Compute for Generative AI: A Framework for Enterprise Workloads arxiv.org/abs/2610.07094 arxiv.org/pdf/2610.07094 arxiv.org/html/2610.07094

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Francesco Minervini, Lorenzo Deltetto, Osman Unsal, Adrian Cristal: SVRF: Efficient Register Storage for Long-Vector Architectures arxiv.org/abs/2610.07078 arxiv.org/pdf/2610.07078 arxiv.org/html/2610.07078

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi: An Empirical Fault Vulnerability Exploration of ReRAM-based Process-in-Memory CNN Accelerators arxiv.org/abs/2610.07029 arxiv.org/pdf/2610.07029 arxiv.org/html/2610.07029

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Xiaoyu Hao, Keren Zhu: FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs arxiv.org/abs/2610.06937 arxiv.org/pdf/2610.06937 arxiv.org/html/2610.06937

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

Linjian Yang, Xinyan Wang, Kunpeng Liu: ElecSafety: Diagnosing Large Language Model Safety Judgments for Microcontroller Boards arxiv.org/abs/2610.06905 arxiv.org/pdf/2610.06905 arxiv.org/html/2610.06905

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 07/10/2026

[2026-10-07 Wed (UTC), 18 new articles found for csAR Hardware Architecture]

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

Harsh Songara, et al.: Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller arxiv.org/abs/2610.06475 arxiv.org/pdf/2610.06475 arxiv.org/html/2610.06475

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

Hayes, Pantazi-Kypraiou, Tziouvaras, Stamoulis, Pathania, Shanker, Floros: Reinforcement Learning-Based Optimization of Workload-Aware Power Delivery Networks arxiv.org/abs/2610.06148 arxiv.org/pdf/2610.06148 arxiv.org/html/2610.06148

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

Mayuresh Warunjikar, Madhav Desai: An ASIC Design Flow for High-Level Synthesis of Asynchronous Circuits arxiv.org/abs/2610.05112 arxiv.org/pdf/2610.05112 arxiv.org/html/2610.05112

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

Seonghun Jung, Sieun Moon, Jiyoung Jeong, Jimin Lee, Jaehyuk Huh: Beyond LLM Serving: Characterizing Vision-Language-Action Workloads for Embodied AI System Design arxiv.org/abs/2610.05062 arxiv.org/pdf/2610.05062 arxiv.org/html/2610.05062

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

Rajatabha Chakraborty, M P Samartha, Vedant Pahariya, Priyesh Shukla: SparseCraft: Agentic Hardware-Software Co-Optimization for Sparse Computing arxiv.org/abs/2610.05037 arxiv.org/pdf/2610.05037 arxiv.org/html/2610.05037

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

Chang Sun, Zhiqiang Que, Dimitrios Danopoulos, Maurizio Pierini, Wayne Luk, Maria Spiropulu: Alkaid: A Compiler Framework for Ultra-Low-Latency Kernels on Hardware arxiv.org/abs/2610.04808 arxiv.org/pdf/2610.04808 arxiv.org/html/2610.04808

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

Maisha Mastora, Dean Sullivan: An Executable Benchmark for LLM-Based HLS Repair:Design Complexity and Repair Underconstraint arxiv.org/abs/2610.03971 arxiv.org/pdf/2610.03971 arxiv.org/html/2610.03971

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 06/10/2026

[2026-10-06 Tue (UTC), 7 new articles found for csAR Hardware Architecture]

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 05/10/2026

Mario Ib\'a\~nez Bolado, Borja P\'erez Pav\'on, Jose Luis Bosque Orero, Julio Ram\'on Beivide: Divide and conquer: Scalable performance and energy in MCM GPUs arxiv.org/abs/2610.03061 arxiv.org/pdf/2610.03061 arxiv.org/html/2610.03061

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 05/10/2026

Wang, Guo, Guo, Guan, Jiang, Zhang, Li, Si, Ainsworth, Jiang: PEEK: Heterogeneous Parallelism for Privileged Error Detection in Safety-Critical Processors arxiv.org/abs/2610.03045 arxiv.org/pdf/2610.03045 arxiv.org/html/2610.03045

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 05/10/2026

William C. Tegge, Jo\~{a}o Paulo Cardoso de Lima, Shouzhi Fang, Jeronimo Castrillon, Alex K. Jones: RAPID: Row-Parallel Arithmetic Processing in DRAM arxiv.org/abs/2610.02502 arxiv.org/pdf/2610.02502 arxiv.org/html/2610.02502

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 05/10/2026

Wajid Ali, Muhammad Hadir Khan, Dalton Gaddy, Matthew Guthaus: Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology arxiv.org/abs/2610.02401 arxiv.org/pdf/2610.02401 arxiv.org/html/2610.02401

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 05/10/2026

Vishnu PS, Ajay Kumar M, Yike Li, Robert Bogdan Staszewski, Deepu John: AdaptViT: Runtime-Adaptive Vision Transformer Deployment on Custom RISC-V arxiv.org/abs/2610.02288 arxiv.org/pdf/2610.02288 arxiv.org/html/2610.02288

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arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 05/10/2026

Kwanhee Lee, Namhoon Lee, Dan Alistarh: Hardware-Native Joint Sparse-Quantization for Trillion-Scale Mixture-of-Experts arxiv.org/abs/2610.02241 arxiv.org/pdf/2610.02241 arxiv.org/html/2610.02241

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